STM32H753 clock setting

Pilous Droip · ‎2019-08-08

Hi friends.

I work with this chip STM32H753, but I set wrong clock.

void SystemClock_Config(void) {
	uint32_t i;
 
	// Enable HSE
	LL_RCC_HSE_Enable();
	// Wait till HSE is ready
	while ((LL_RCC_HSE_IsReady()) == 0)
		;
	//PLL1 - external quartz
	LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
 
	//PLLM = 2
	LL_RCC_PLL1_SetM(2);	// 25MHz / 2 = 12500000Hz
	LL_RCC_PLL1_SetN(64);	// 12500000 * 64 = 800000000Hz
	LL_RCC_PLL1_SetP(2);	// 800000000 / 2 = 400000000Hz
	LL_RCC_PLL1_SetQ(2);
	LL_RCC_PLL1_SetR(2);
 
	/* Configure PLL PLL1FRACN */
	LL_RCC_PLL1_SetFRACN(0);
 
	/* Select PLL1 input reference frequency range: VCI */
	LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);
 
	/* Enable PLL1Q Clock output. */
	LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
 
	//__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
	LL_RCC_PLL1Q_Enable();
 
	/* Enable PLL1R  Clock output. */
	// __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
	LL_RCC_PLL1R_Enable();
 
	/* Enable PLL1FRACN . */
	//__HAL_RCC_PLLFRACN_ENABLE();
	LL_RCC_PLL1FRACN_Enable();
 
	/* Enable the main PLL. */
	//__HAL_RCC_PLL_ENABLE();
	RCC->CR |= RCC_CR_PLLON;
	while ((LL_RCC_PLL1_IsReady()) == 0)
		;
 
	//RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
	LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
 
	//RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
	LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
 
	//Set PLL1 as source of SYSCLK
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
 
	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
		;
 
	//Configuration - D1PPRE
	LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_2);
 
	//Configuration - D2PPRE1
	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_8);
 
	//Configuration - D2PPRE2
	LL_RCC_SetAPB2Prescaler(LL_RCC_APB3_DIV_2);
 
	//Configuration - D3PPRE
	LL_RCC_SetAPB4Prescaler(LL_RCC_APB3_DIV_2);
 
	LL_Init1msTick(400000000);
	LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);
	LL_SetSystemCoreClock(400000000);
	LL_RCC_SetTIMPrescaler(LL_RCC_TIM_PRESCALER_TWICE);
// clock enable
	LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
}

And my program stay here:

while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
		;

Any idea, what is wrong?

waclawek.jan · ‎2019-08-08

> /* Select PLL1 input reference frequency range: VCI */

> LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);

From https://github.com/STMicroelectronics/STM32CubeH7/blob/master/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_rcc.h :

/**
  * @brief  Set PLL1 VCO OutputRange
  * @note   This API shall be called only when PLL1 is disabled.
  * @rmtoll PLLCFGR        PLL1VCOSEL       LL_RCC_PLL1_SetVCOOuputRange
  * @param  VCORange This parameter can be one of the following values:
  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE
  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
  * @retval None
  */

What's exactly the point of using a "library" here?

JW

Pilous Droip · ‎2019-08-08

I don't understand.

I modificated it, but problem is the same.

void SystemClock_Config(void) {
	uint32_t i;
 
	LL_FLASH_SetLatency(LL_FLASH_LATENCY_6);
 
	if (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_6) {
		; // -todo- failure
	}
 
	// LSI
	LL_RCC_LSI_Enable();
 
	// Enable HSE
	LL_RCC_HSE_Enable();
 
	// Wait till HSE is ready
	while ((LL_RCC_HSE_IsReady()) == 0)
		;
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
 
	//PLL1 - external quartz
	LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
 
	//PLLM = 2
	LL_RCC_PLL1_SetM(2);	// 25MHz / 2 = 12500000Hz
	LL_RCC_PLL1_SetN(64);	// 12500000 * 64 = 800000000Hz
	LL_RCC_PLL1_SetP(2);	// 800000000 / 2 = 400000000Hz
	LL_RCC_PLL1_SetQ(2);
	LL_RCC_PLL1_SetR(2);
 
	/* Configure PLL PLL1FRACN */
	LL_RCC_PLL1_SetFRACN(0);
 
	/* Select PLL1 input reference frequency range: VCI */
	LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_8_16);
 
	//__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
	LL_RCC_PLL1Q_Enable();
 
	/* Enable PLL1R  Clock output. */
	LL_RCC_PLL1R_Enable();
 
	/* Enable PLL1FRACN . */
	LL_RCC_PLL1FRACN_Enable();
 
	//RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
	LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
 
	//RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
	LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
 
	LL_RCC_PLL1_Enable();
	while (LL_RCC_PLL1_IsReady() == 0)
		;
 
	//Set PLL1 as source of SYSCLK
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
		;
...........................
}

Program crash on this line>

	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
		;

waclawek.jan · ‎2019-08-08

Sorry for bad quote.

Check the content of relevant registers. Output PLL to MCO and observe. Do you set FLASH latency appropriately to the clock? Is voltage regulator set appropriately?

JW

Pilous Droip · ‎2019-08-08

I set register RCC->CFGR bits SW[2:0] to value 0x03.

LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);

And value SWS[5:3] is still 0. And it must be to set: 0x03. Everything is set good. Only this register is wrong.

Problem will with STOPWUCK. I hope.

Pilous Droip · ‎2019-08-08

I rewrite this problem to register....

	RCC->CR |= RCC_CR_HSEON;
	// Wait till HSE is ready
	while ((RCC->CR & RCC_CR_HSERDY) == 0)
		;
 
	//RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
	RCC->PLLCKSELR |= RCC_PLLCKSELR_PLLSRC_HSE;
 
	//PLLM = 2
	RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_5; //0
	RCC->PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_4; //0
	RCC->PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_3; //0
	RCC->PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_2; //0
	RCC->PLLCKSELR |= RCC_PLLCKSELR_DIVM1_1; //1
	RCC->PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_0; //0
 
	//PLL1DIVR     bits
	//DIVN1[8:0]  0  - 8   PLLN = 400
	//DIVP1[6:0]  9  - 15  PLLP = 2
	//DIVQ1[6:0]  16 - 22  PLLQ = 2
	//DIVR1[6:0]  24 - 30  PLLR = 2
	RCC->PLL1DIVR |= 0x0101023F;
 
	/* Configure PLL  PLL1FRACN */
	RCC->PLL1FRACR = 0;
 
	/* Select PLL1 input reference frequency range: VCI */
	RCC->PLLCFGR |= RCC_PLLCFGR_PLL1RGE_3;
 
	/* Disable PLL System Clock output. */
	RCC->PLLCFGR &= ~RCC_PLLCFGR_DIVP1EN;
 
	/* Disable PLL1Q Clock output. */
	RCC->PLLCFGR &= ~RCC_PLLCFGR_DIVQ1EN;
 
	/* Disable PLL1R  Clock output. */
	RCC->PLLCFGR &= ~RCC_PLLCFGR_DIVR1EN;
 
	/* Disable PLL1FRACN . */
	RCC->PLLCFGR |= RCC_PLLCFGR_PLL1FRACEN;
 
	/* Enable the main PLL. */
	RCC->CR |= RCC_CR_PLLON;
	while ((RCC->CR & RCC_CR_PLL1RDY) == 0)
		;
 
	RCC->D1CFGR |= RCC_D1CFGR_HPRE_3; //1
	RCC->D1CFGR &= ~RCC_D1CFGR_HPRE_2; //0
	RCC->D1CFGR &= ~RCC_D1CFGR_HPRE_1; //0
	RCC->D1CFGR &= ~RCC_D1CFGR_HPRE_0; //0
 
	RCC->D1CFGR &= ~RCC_D1CFGR_D1CPRE_3; //0
	RCC->D1CFGR &= ~RCC_D1CFGR_D1CPRE_2; //0
	RCC->D1CFGR &= ~RCC_D1CFGR_D1CPRE_1; //0
	RCC->D1CFGR &= ~RCC_D1CFGR_D1CPRE_0; //0
 
	RCC->CFGR &= ~RCC_CFGR_SW_2; //0
	RCC->CFGR |= RCC_CFGR_SW_1; //1
	RCC->CFGR |= RCC_CFGR_SW_0; //1
 
	while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1)
		;

And problem is the same. Program crash here.

while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1)
		;

Pilous Droip · ‎2019-08-13

Here is my function code for clock. :)

	LL_APB4_GRP1_EnableClock(LL_APB4_GRP1_PERIPH_SYSCFG);
 
	LL_RCC_HSI_Enable();
	while(LL_RCC_HSI_IsReady() == 0)
		;
 
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
	while( LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_HSI)
		;
 
	LL_RCC_HSI48_Enable();
	while (LL_RCC_HSI48_IsReady() == 0)
		;
 
	/* Configure voltage regulator */
	//Set the highest core voltage (Scale 1)
	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
	//Wait for LDO ready
	while (LL_PWR_IsActiveFlag_VOS() == 0)
		;
 
	LL_RCC_HSE_DisableBypass();
	LL_RCC_HSE_Enable();
	while(LL_RCC_HSE_IsReady() != 1)
		;
 
	//RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
	LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
 
	//PLLM = 2
	LL_RCC_PLL1_SetM(2);
	LL_RCC_PLL1_SetN(64);
	LL_RCC_PLL1_SetP(2);
	LL_RCC_PLL1_SetQ(2);
	LL_RCC_PLL1_SetR(2);
 
	// /* Configure PLL  PLL1FRACN */
	LL_RCC_PLL1_SetFRACN(0);
 
	/* Select PLL1 input reference frequency range: VCI */
	LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
 
	LL_RCC_PLL1P_Enable();		/* Enable PLL System Clock output. */
	LL_RCC_PLL1Q_Disable();		/* Disable PLL1Q Clock output. */
	LL_RCC_PLL1R_Disable();		/* Disable PLL1R  Clock output. */
	LL_RCC_PLL1FRACN_Disable();	/* Disable PLL1FRACN . */
 
	/* Enable the main PLL. */
	LL_RCC_PLL1_Enable();
	while (LL_RCC_PLL1_IsReady() == 0)
		;
 
	LL_RCC_SetSysPrescaler(LL_RCC_SYSCLK_DIV_1);
	LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
 
	LL_RCC_SetAHBPrescaler(LL_RCC_AHB_DIV_2);
	LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_8);
	LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
	LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_2);
 
	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
	while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
		;
 
	LL_Init1msTick(400000000);
	LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);
	LL_SetSystemCoreClock(400000000);
	LL_RCC_SetTIMPrescaler(LL_RCC_TIM_PRESCALER_TWICE);