HSI to PLLCLK set to max frequency causing hard faults

[kikib]

Hey, I'm having some issues with setting up clocks for my STM32F411CEU custom board with HAL.

Using PLLCLK from HSI ends up with Hardfault, around where RCC is being configured.

The only way I don't get hardfaults is:

1) if I set System Clock Mux to HSI instead of PLLCLK, but then it runs on 16Mhz which is way too slow for me.

2) I set System Clock Mux to PLLCLK and clock to something lower than 50Mhz.

I tried making an empty project, just initialization, and have the same issues. This happens on two different boards. I'm starting to suspect that JLCPCB sent me some fake ICs..

Shouldn't internal clock be the most "safe" and "should always work" option?

Been bashing my head on the table for few hours now, trying every possible combination but nothing works.

Thanks!

[RomainR.]

Hi @kikib 

Yes the HSI still works if it is not turned off in the code. It is the default clock source after the RESET.
Are you using CubeMX to generate your configuration? Can you share your code?
Before suspecting the STM32F4 on your board, I recommend you to check what is the source of the Hard Fault when initializing the RCC.
- The PLL is misconfigured, or you are trying to change its parameters without turning it off first?
- You are trying to start the PLL on a clock source that is not turned on?
- The Flash latency is not configured? For a SYCLK=50MHz you should have 1WS.
Maybe you should try the following example:
STM32Cube_FW_F4_V1.28.1\Projects\STM32F411RE-Nucleo\Examples\RCC\RCC_ClockConfig

And confirm that your STM32F411 starts well with the HSI+PLL at 100MHz frequency?

Best regards,

Romain,

[TDK]

> STM32F411CEU custom board

Care to share your schematic? VDDA shorted to VDD? VSSA shorted to VSS? Appropriate bulk and decoupling capacitors present? VCAP cap present?

If it's a board design issue, you won't be able to fix it in software.

[Tesla DeLorean]

Flash wait states? Assume sweetspot around 24-27 MHz for Flash array, so one additional wait state at 50 MHz should be fine.

Issue with VCAP? Should be around 1.25V with around 4.7uF total capacitance across multiple pins

[kikib]

Hey thanks for the help!

Here is the schematics:

One mention is that the HSE is not present. About the VCAP, I just realized that I did not place it. Could this somehow influence the RCC?

[kikib]

Hey Romain, thanks for reply. The hardfault is somewhat erratic, as it does not always happen at the same spot, so it's hard to pinpoint what the issue is.

I attached .ioc file I'm currently using. Keep in mind, that I had same issue when I started with an empty project (no custom configuration at all).

Regarding your "points", HSI->PLL is working fine with system frequencies <=50Mhz. So I would assume everything you stated should be working.

I will try the example you provided, thank you!

[TDK]

If VCAP is not present, the chip will not be able to run reliably, if at all. That is the issue. The capacitor on VCAP stabilizes/decouples the internal voltage rail. Without that, hard faults and other weirdness can be expected to occur, especially as the chip uses more power.

Getting started with STM32F4xxxx MCU hardware development - Application note

You can take a look at the design guide as well. But other than VCAP the schematic looks okay.

[STOne-32]

Dear @kikib ,

as mentioned by @TDK @without VCAP connected to a 4,7uF capacitor , not chance to get the MCU working in reliable way and PLL active .

Ciao

STOne-32