STM32H745 FMC acces to external NOR with timing from RM0399 does not work (works only with burst, but not non-burst)

[dze.1]

Hallo,

I'm using a STM32H745, that shall access an external NOR flash with the timing recommended by ST at the reference manual RM0399 on page 875.  I did exactly reproduce this timing setting, but no access will be generated on the FMC pins.

When I change one single bit in this configuration (bit 8 = BURSTEN set to 1) the access works, but of course as BURST access. My intention is a non-burst access.

However, that proves that all other settings are basically ok, including pin configuration, providing clock to the FMC and generating read/write access to the FMC bank 1.

The issue can be reproduced on two ways:

First via debugger.

After configuring the pins and switching the FMC clock on, set the register BCR1 and BTR1 and generate access via memory browser.

Second with the following code:

{
  // Peripheral clock enable
  LL_RCC_SetFMCClockSource( LL_RCC_FMC_CLKSOURCE_HCLK );
  LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_FMC );
 
  // Pin configuration
  for( uint32_t i = 0; i < ARRAYSIZE(Pin_FMC); i++ )
  {
    Pin_FMC[i].Setup();
  }
 
  FMC_NORSRAM_TypeDef* const Dev = FMC_NORSRAM_DEVICE;
  uint32_t const Bank = FMC_NORSRAM_BANK1;
 
  __FMC_NORSRAM_DISABLE( Dev, Bank );
 
  // Initialize SRAM control interface
  MODIFY_REG( Dev->BTCR[Bank],
 
              // --- field mask ---
              // FMC_BCRx_MBKEN     bank will be enabled later
              FMC_BCRx_MUXEN     |
              FMC_BCRx_MTYP      |
              FMC_BCRx_MWID      |
              FMC_BCRx_FACCEN    |
              FMC_BCRx_BURSTEN   |
              FMC_BCRx_WAITPOL   |
              FMC_BCRx_WAITCFG   |
              FMC_BCRx_WREN      |
              FMC_BCRx_WAITEN    |
              FMC_BCRx_EXTMOD    |
              FMC_BCRx_ASYNCWAIT |
              FMC_BCRx_CPSIZE    |
              FMC_BCRx_CBURSTRW  |
              FMC_BCR1_CCLKEN    |
              FMC_BCR1_WFDIS,
              // FMC_BCR1_BMAP     bank mapping default value is used
              // FMC_BCR1_FMCEN    FMC will be enabled later
 
              // --- field values ---
              FMC_DATA_ADDRESS_MUX_ENABLE      |
              FMC_MEMORY_TYPE_NOR              |
              FMC_NORSRAM_MEM_BUS_WIDTH_16     |
              FMC_NORSRAM_FLASH_ACCESS_ENABLE  |
              FMC_BURST_ACCESS_MODE_ENABLE     | // must be set to one, why?
              FMC_WAIT_SIGNAL_POLARITY_LOW     | // not used
              FMC_WAIT_TIMING_BEFORE_WS        | // don't care
              FMC_WRITE_OPERATION_ENABLE       |
              FMC_WAIT_SIGNAL_DISABLE          | // no effect in async mode
              FMC_EXTENDED_MODE_DISABLE        |
              FMC_ASYNCHRONOUS_WAIT_DISABLE    | // wait signal not used
              FMC_PAGE_SIZE_NONE               | // no effect in async mode
              FMC_WRITE_BURST_DISABLE          | // no effect in async mode
              FMC_CONTINUOUS_CLOCK_SYNC_ONLY   |
              FMC_WRITE_FIFO_DISABLE
            );
 
  // Set SRAM timing parameters
  MODIFY_REG( Dev->BTCR[Bank + 1],
              FMC_BTRx_ADDSET  | // --- field mask ---
              FMC_BTRx_ADDHLD  |
              FMC_BTRx_DATAST  |
              FMC_BTRx_BUSTURN |
              FMC_BTRx_CLKDIV  |
              FMC_BTRx_DATLAT  |
              FMC_BTRx_ACCMOD,
              (2 << FMC_BTRx_ADDSET_Pos)  | // --- field values ---
              (1 << FMC_BTRx_ADDHLD_Pos)  |
              (1 << FMC_BTRx_DATAST_Pos)  |
              (1 << FMC_BTRx_BUSTURN_Pos) |
              (3 << FMC_BTRx_CLKDIV_Pos)  | // FMC_CLK period = 4 × fmc_ker_ck periods (240 MHz / 4 = 60 MHz)
              (1 << FMC_BTRx_DATLAT_Pos)  | // Data latency of 2 FMC_CLK clock cycles for first burst access
              FMC_ACCESS_MODE_A
            );
 
  __FMC_NORSRAM_ENABLE( Dev, Bank );
 
  // Enable FMC Peripheral
  __FMC_ENABLE();
 
  volatile uint16_t* const BankAddr = reinterpret_cast<volatile uint16_t*>(0x60000000);
  volatile uint16_t r = *BankAddr; // generate read access
  *BankAddr = 0xA5A5;              // generate write access
}

My questions:

Asynchronous access to NOR should work in non-burst mode as well as in burst mode.

Why does the non-burst example from ST not work?

How can a non-burst access achieved?

That you very much in indeed.

[Tesla DeLorean]

Caching or MPU configuration of memory region?​

[dze.1]

Both caches are disabled and the MPU is not used.

[dze.1]

I have now switched on the MPU and configured the NOR-memory space as device.

The BURST read and write access is working perfect, but when configuring the bank for non-burst (bit 8 = BURSTEN set to 0) no access happens.

The MPU is configured according to the NOR example FMC_NOR for STM32H743 from CubeIDE. I copied the MPU initialising sequence from this project:

{
    HAL_MPU_Disable();
 
    // Configure the MPU attributes as device for NOR
    MPU_Region_InitTypeDef MPU_InitStruct =
    {
      .Enable = MPU_REGION_ENABLE,
      .Number = MPU_REGION_NUMBER0,
      .BaseAddress = reinterpret_cast<uint32_t>(BankAddr),
      .Size = MPU_REGION_SIZE_16MB,
      .SubRegionDisable = 0x00,
      .TypeExtField = MPU_TEX_LEVEL0,
      .AccessPermission = MPU_REGION_FULL_ACCESS,
      .DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE,
      .IsShareable = MPU_ACCESS_SHAREABLE,
      .IsCacheable = MPU_ACCESS_NOT_CACHEABLE,
      .IsBufferable = MPU_ACCESS_BUFFERABLE
    };
    HAL_MPU_ConfigRegion( &MPU_InitStruct );
 
    HAL_MPU_Enable( MPU_PRIVILEGED_DEFAULT );
  }

Note: The FMC_NOR example project for STM32H743 from CubeIDE is using the FMC in non-multiplexed mode where I have to use the FMC in multiplexed mode.