2024-07-08 09:53 AM
... or something I don't understand?
Looking at RM0468, 2.1 System Architecture "Table 2. Bus-master-to-bus-slave interconnect" shows that DMA1 and DMA2 have access to basically everything except TCM, including APB4 peripherals and SRAM4.
Is there some hidden feature to let DMA1 / DMA2 actually access "D3 domain"? If yes, how?
Am I reading that wrong, or is it another documentation blunder?
It would be so helpful to use DMA1/2 with SAI4...
2024-07-08 10:05 AM
Okay, at least DMA1/2 can access SRAM4!
Now only the "APB4 peripherals" entry is wrong?
2024-07-08 11:00 AM
Seem to recall APB4 / GPIO / RAM4 has it's own DMA unit, BDMA on H7's ?
2024-07-08 01:31 PM
Not all 'H7 created equal.
Should be complete connectivity from D2 to D3 in this sub-family:
JW
2024-07-09 03:56 AM
@Tesla DeLorean yes, BDMA can handle D3 internal stuff. BDMA is a little different from DMA1/2, mainly working without FIFO, but I can probably live with that
@waclawek.jan it looks per DS/RM as if DMA1/2 could access the D3 peripherals, but they cannot because the DMAMUX for DMA1/2 has no connection to the D3 peripherals. That's a little misleading, at least.
At least DMA1/2 can access SRAM4 in D3, that might help.
2024-07-09 04:08 AM
> DMAMUX for DMA1/2 has no connection to the D3 peripherals
That does not mean that DMA1/2 can't *access* D3 peripherals. DMA *requests* (aka triggers) and DMA *transfers* are not bound to each other, even if that's the most common usage (there may be a logical bound, though, which may be not that obvious - e.g. a request).
For example, you can use TIM4 to trigger DMA1 to transfer from memory into SPI6 DR, thus initiating an entirely correct SPI Tx.
Maybe the SAI4->TIM5_ETR interconnection can be abused for what you intend to do? I don't use this chip and yes, it's apparently a beast.
JW
2024-07-09 04:54 AM
> Maybe the SAI4->TIM5_ETR interconnection can be abused for what you intend to do?
That sounds interesting, I'll check...