STM32H7 PSSI discrepancy between Datasheet and ref.manual

Michal Dudka · ‎2025-01-23

Hi,
Ref.manual (RM0477 Rev 8) in chapter 32.3.3 PSSI clock says

In case when PSSI transmitting data, then RDY pin is input.
Datasheet (DS14360 Rev 2) shows setup and hold time of RDY pin (input) referenced to rising edge as well as data pins (outputs).

I think that's a contradiction. So how is it really and to which edge do RDY setup and hold times relate ?
Thanks,
Michal Dudka

KDJEM.1 · ‎2025-01-23

Hello @Michal Dudka,

Thank you for bringing this issue to our attention.

I will check internally this issue between the reference manual and datasheet. And, I will come back to you with details as soon as possible.

Thank you.

Kaouthar

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SofLit · ‎2025-01-23

Hello,

Do you mean the description in the reference manual is inverted? and should be:

When CKPOL = 0
– Input pins are sampled on PSSI_PDCK rising edge
– Output pins are driven on PSSI_PDCK rising edge
• When CKPOL = 1
– Input pins are sampled on PSSI_PDCK falling edge
– Output pins are driven on PSSI_PDCK falling edge

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Michal Dudka · ‎2025-01-23

As I understand the timing diagram, that's how it should be. But naturally I have no idea which information is correct one. And the way to find it out is somewhat difficult (I would have to sweep the input signal and verify on the STM side when it interpreted it correctly)