STM32H7 DMA Speed

[AlexSmart]

How fast is DMA on STM32H7 mcus? I didnt find any description on how many ticks takes one transaction.

I linked DMA to a timer, transfer from memory to port. With system clock 480 MHz and timer DMA request frequency 40 MHz it doesnt seem to work fast enough. 20 MHz DMA requests works fine...

Memory buffer located in SRAM1, DMA1 is used, D-cache disabled.

[TDK]

It depends on many things including where the data is going and how busy the rest of the system is with the relevant buses. Generally, in the tens of MBps, which is consistent with your observations.

Access to GPIO pin registers is generally slower than other things as they're in the D3 domain.

[AlexSmart]

I see. So if want to reduce latency I need to put My memory buffer in SRAM4, and use BDMA instead of DMA1?

[TDK]

As far as I understand, yes, that should help considerably. Please report results if you check.

[Tesla DeLorean]

Quick hack on the H723 with a simple Mem-to-Mem transfer from SRAM4 to GPIOB->BSRR, looked to be 10 MHz (5 MHz square wave from pattern buffer)

[AlexSmart]

I got 16.6MHz square (33.2 MHz rate).

Before trying BDMA I want to make sure I got things right. Page 16 of AN4891 says one transfer in my case should take 25 cycles. 25 SYSCLK cycles? 23 AHB1 cycles + 2 AHB4 cycles? Either way DMA request rate should be lower than it is. 33.2*25 = 830 MHz...

[Danish1 · Accepted solution]

I think you might be misreading that table. My reading of it is that e.g. Master Type DMA1 to slave Type APB4 Peripheral has Route=23 and you have to look at footnote 3 to see that Route 23 means 2 = via AHB bus matrix in D2 and 3 = via AHB bus matrix in D3

So it is in clock domains 2 and 3 via the AHB matrix. I guess it might take one clock cycle of the faster clock domain plus two cycles of the slower clock domain worst-case.

Not that it will take 23 cycles!

Regards, Danish

[AlexSmart]

I see, my bad. You are saying, that

 I guess it might take one clock cycle of the faster clock domain plus two cycles of the slower clock domain worst-case.

But it still doesnt match my real value. Is there a document that help me find out exactly how many clock cycles it will take?

By the way SRAM4 snd BDMA showed slower results (27 MHz approx instead 33.2)

[Tesla DeLorean]

BDMA did seem slower than it should be, and lacked the trigger sources I'd prefer to use. The bus should have been 275 MHz, unless I missed something, or the H723 is a quirky design. I would have thought the Mem-to-Mem would have pegged the maximum transfer rate.

Not sure there's a document, but given two transactions, minimum of 8 cycles wouldn't surprise me.

[waclawek.jan]

Generally, AN2548 applies to BDMA and AN4031 to DMA.

The devil is of course in the details, of which in the 'H7 are just too many.

JW