STM32H7 datasheet SPI characteritics are not clear

[Gpeti]

Hello,

The SPI characteristics in the STM32H753 datasheet are not clear (for me at least):

What does "slave receiver mode" means ? Is it half-duplex or simplex communication ?

Right now I'm able to communicate between two STM32H7 Nucleo boards connected in SPI full duplex, prescaler 2 and maximum clocks, so at the maximum SPI frequency, close to 100MHz, but for this I am doing only transmission on master side (call to HAL_Transmit) and reception on slave side (call to HAL_Receive). Calling HAL_TransmitReceive does not work.

Now I am writing my own drivers and I am digging deeper in this issue.

In full duplex the slave is both transmitting and receiving so, except the software overhead needed to write the data in SPI slave transmit fifo I don't understand the difference between a slave that is only receiving and a slave that is transmitting and receiving.

Could you clarify ?

[Tesla DeLorean]

>>What does "slave receiver mode" means ? Is it half-duplex or simplex communication ?

It means you're the SLAVE device on the bus, and thus the sense of MISO/MOSI changes because you're not the *master*. You also become dependent on the CS/NSS state to know that it is your device that is being talked too, and also the SCLK which is now an INPUT.

The bus is still symmetrical, data goes in both directions.

Why is the frequency different? Probably because the alien clock/data paths must be resynchronized into the STM32 clock domains.

[Gpeti]

Actually I've explained in details my issue on SO:

https://stackoverflow.com/questions/57874074/about-the-limitation-of-stm32h7-spi-in-slave-mode

[Gpeti]

Sorry my question was about slave mode transmitter

[SF??r]

In your configuration you could communicate with 31 or 29 MHz only (depense on supply voltage).

You could use up to 100 MHz if each Nucleo-Board has a Receiver and a Sender SPI (two SPIs per Board).

[Gpeti]

Thank you for your answer. What I don't understand is: why ? I mean that SPI slave in full duplex is by defintion sending and receiving at the same time. (may be it is sending crap or only 0s but it is still sending). So why the STM32 in slave mode receive at 100MHz but not send ? Is it linked to the internal behaviour of the peripheral, like the shift register is not able to be fed fast enough by the TxFIFO ?

[SF??r]

The bus should be fast enough. Delays are between SCL in to MISO data settling...