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STM32H7 ADC3 over BDMA only writing to buffer once

Associate II

I am working with a STM32H723 micro, capturing 2048 samples of data on ADC3. The ADC is triggered by the overflow of TIM1 and transfers samples successfully the first time HAL_ADC_Start_DMA(&hadc3, (uint32_t*)adc_buf, ADC_BUF_LEN); is called.

In the HAL_ADC_ConvCpltCallback function, the ADC is stopped and a flag is raised to indicate new data is ready for processing in the main loop.



void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc){
new_data = 1;



The data is processed in the main loop and at the end of the processing function, HAL_ADC_Start_DMA(&hadc3, (uint32_t*)adc_buf, ADC_BUF_LEN); is called again to restart the ADC. 

The problem appears the next time the HAL_ADC_ConvCpltCallback fires. The data in the output buffer stays the same every loop after the first. The ADC is definitely running, as the callback fires regularly at the expected frequency, but the data is never updated.

The destination buffer is in the SRAM4 section as required for BDMA and the transfer does complete successfully, but only the once. 


I can't remember what it was, but I started using BDMA for ADC3 on the same STM32, but there was some problem, so I changed to DMA 1 or 2 and then it worked... but using DMA in circular mode here.

Which function is actually calling HAL_ADC_ConvCpltCallback() ?

I'm trying to avoid using the regular DMA (mainly out of stubbornness) but I'll give it a go if nothing else works. HAL_ADC_ConvCpltCallback() is being called by the BDMA IRQ - see call stack below.


It's called by the BDMA IRQ handler even in the instances where the destination buffer isn't overwritten. So either the DMA transfer is taking place and the values just aren't changing, or the DMA IRQ is getting called before the transfer takes place - perhaps the interrupt flag isn't cleared after the first set of transfers?


I have no idea, the DMA HAL functions are quite good, maybe there's some ADC things you have to reset?

Are you using any caches?


Here's my ADC stuff, running on a H723 Nucleo and a H735 Discovery Kit.

But it's a different ADC application than what you need. DMA is collecting AD data all the time in the background, and every now and then this data is checked. Regularly, but without any timing constraint.

Chief II

You can do the D-cache invalidation on just the ADC_DMA_BUF_SIZE/2. Just ensure that the half buffer is also aligned to 32 bytes.