2020-04-15 05:57 AM
Hi everyone
I'm trying to get the ADC1 running with a DMA transfer on the STM32H757ZI. The goal is to measure 10 channels with 8 samples each and transfer these measurements to a separated SRAM1 buffer with DMA, each time the conversion sequence has been finished.
The problem I have is, that the ADC1 seems to work properly, since I'm reading some data in the DR, but the DMA transfer is never initiated. I have enabled the EOC and EOS interrupts, the corresponding ISR clears the EOC / EOS bits. I have set the DMNGT to DMA circular mode, which I assume enables the DMA functionality for the ADC peripheral. The transfer complete interrupt for the DMA is triggered, but no data is written to the buffer...
In addition, I have used the following DMA settings:
However, there's no data copied into the SRAM1 buffer... what am I missing here? Is there some additional setting I have to enable?
edit: I've set up the buffer according to this link :
https://community.st.com/s/article/FAQ-DMA-is-not-working-on-STM32H7-devices
I'm using Solution 2 - placing the buffer in a different memory region.
Regards
Daniel.
2020-05-07 10:32 AM
Hi and sorry for this late reply.. I have setup the ADC without DMA for now... we are developing other parts and are a bit under pressure (as usual)... I'll come back to this as soon as I'm working on the ADC again..
Thanks and regards
Daniel.
2021-12-10 02:22 AM
Hi,
I am having the same problem, did you find something?
2021-12-10 04:56 AM
Unfortunately not. We have decided to not use the DMA with the ADC.
2022-05-09 06:08 AM
Hi DSchl.1,
I faced the same problem.
I do not know if you solve the problem, but you should invalidate cache when DMA transfer completed by using "SCB_InvalidateDCache_by_Addr" function.
All the bests,
Savas
2022-05-10 01:34 PM
Wrong. The invalidation must be done before starting the reception on a particular buffer by DMA.
An instruction of proper cache management:
Topic about the cache eviction:
https://community.st.com/s/question/0D50X0000C9hGozSQE/weird-cache-writeback-behavior-for-stm32f7508
2022-05-17 01:53 AM
Hi Piranha,
Thank you for your answer. I will check them.
I align the DMA buffers so that when invalidation no other addresses affected.
After DMA transmission completed. I only invalidate cache with that dma buffer. In this way no need to clean the cache. Cache reloads with new values which was updated by DMA transfer with new values.
This works with stm32h750 and stm32h753/743 devices perfectly.
Will it cause any problems that i can not see yet?
All the bests,
Savas