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mathieuM
Associate II
March 22, 2024
Solved

STM32H563 Revision Z Creates a HardFault in the UCPD Library.

  • March 22, 2024
  • 1 reply
  • 4264 views
With revision Z of the STM32H563VIT6, which looks to be an older revision of the MCU, we get a HardFault issue in the UCPD library. We noticed the issue with revision Z, but revision X is working as expected (see errata in attachments)!
mathieuM_0-1711120814750.png
mathieuM_1-1711120814752.pngmathieuM_2-1711120814754.png

 

When connecting a device through USB-C, the MCU goes in a HardFault when setting Rp resistors to SinkTxNG.
In the STM UCPD library, I see that there is some added code to manage older revision of the component, and the line with the red arrow creates the HardFault.
mathieuM_3-1711120814756.png
It seems that the MCU is not able to access "pUCPD_TRIM_1A5_CC1" value in non-volatile memory at address 0x08FFF844, even though there is a value at this address if I manually look for it in the flash.
mathieuM_4-1711120814757.png
What could create this HardFault?
Is there something we can do to fix this HardFault or should we discard all revisions other than the X?
    This topic has been closed for replies.
    Best answer by STOne-32

    Dear @mathieuM ,

    Thank you for the question, I do not have a board now to check, but Indeed I confirm that RevX is the latest revision in production and fixes few major limitations - you can see in the first table between A, Z and X.   May be you hit this Knowledge Article case as that @Address is impacted by RO data if you can check and let me know : How to avoid a hard fault when ICACHE is enabled o... - STMicroelectronics Community

    Hope it helps You.

    STOne-32

    1 reply

    STOne-32
    STOne-32Best answer
    ST Technical Moderator
    March 22, 2024

    Dear @mathieuM ,

    Thank you for the question, I do not have a board now to check, but Indeed I confirm that RevX is the latest revision in production and fixes few major limitations - you can see in the first table between A, Z and X.   May be you hit this Knowledge Article case as that @Address is impacted by RO data if you can check and let me know : How to avoid a hard fault when ICACHE is enabled o... - STMicroelectronics Community

    Hope it helps You.

    STOne-32

      M
      mathieuMAuthor
      Associate II
      March 22, 2024

      Hi,

      I tested what is recommended in the link you sent, and it fixed the issue.

      The HardFault was indead created because of the ICACHE and access to RO memory areas.

      Thank you so much for your quick response!

      Best,

      MM

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