STM32H5 PSSI RDY pin setup and hold times verification

Michal Dudka · ‎2025-01-23

Hi,

STM32H533 datasheet (DS14539 Rev 2) in table 88 says that RDY input setup and hold time are both 0.5ns. From my naive point of view it looks like superb value (RDY have to be stable only +-0.5ns around CLK edge). Isn't that a typo ? (STM32H7 PSSIs hold time is about 5.5ns)

Thanks,
Michal Dudka

SofLit · ‎2025-01-23

Hello,

I'm checking internally if it's the same timing as STM32H7R/S product.

Most probably the issue is on "RDY input hold time" timing (need to check).

From STM32H7S datasheet:

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
PS: This is NOT an online support (https://ols.st.com) but a collaborative space. So please be polite in your reply. Otherwise, it will be reported as inappropriate and you will be permanently blacklisted from my help/support.

SofLit · ‎2025-01-23

Hello,

After an internal check, all the values of H5 in the datasheet are correct while for H7R/S:

th(RDY) : the minimum RDY input hold time is 0ns and not 5.5ns.

New internal ticket for issue follow up on H7RS: 201229.

Thank your for your valuable contribution.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
PS: This is NOT an online support (https://ols.st.com) but a collaborative space. So please be polite in your reply. Otherwise, it will be reported as inappropriate and you will be permanently blacklisted from my help/support.

Michal Dudka · ‎2025-01-23

Great. Is this value verified by measurement? I have preliminary observations from which it seems that RDY signal deasserted during CLK edge (asserted 4.9ns after CLK edge) is interpreted as asserted. But I haven't tested it hard enough to say for sure. In a week or two, I might get back to you with that... unless I find a bug somewhere in my code.