How does FDCAN time stamping work exactly on the STM32H7 ?

[K M]

The FDCAN module generates timestamps for sent and received messages, and you can configure it to use TIM3 as the source. Unfortunately, the documentation is rather thin, so I am left with a few questions:

• Do TIM3 and FDCAN need to run from the same clock or are they synchronized?
• What triggers the timestamp? I suspect this is the SOF bit, and it is sampled once every normal time quantum, so that the trigger resolution is one time quantum
• One probably should not use the timer overflow flag in the CAN module when using TIM3, but check directly in the timer?
• Is there a recommended sequence to get FDCAN time quanta and TIM3 aligned, or should we just run TIM3 with a higher frequency?

[ppedro]

Hello,

can anybody answer the above questions? I dont find any information on how to configure using external CLK source for FDCAN RX timestamp (FDCAN_TIMESTAMP_EXTERNAL). Any advises are appreciated.

Thanx.

Best regards,

peter

[pravee123]

Hello brother 

I have one doubt im doing with rx timestamping I properly configured with 8 prescalar and freq is 64MHZ as per this my wraparound callback have to execute every 8millisec but it is executing for every 1.2sec I used internal rx time stamp fdcan Can please suggest me where I'm doing wrong

[tachibana-44]

Hello,

> Do TIM3 and FDCAN need to run from the same clock or are they synchronized?

No, they don't. See Figure 732. The FDCAN system has two different clock domain. CAN core is drived by fdcan_tq_ck in Kernel clock domain CCU controled. The others are drived in APB clock domain. The TIM3 is connected by fdcan1_ts which is the APB clock domain so that it is not synchronized CAN core.

> What triggers the timestamp? I suspect this is the SOF bit, and it is sampled once every normal time quantum, so that the trigger resolution is one time quantum.

Yes and No. See "Timestamp generation" in Page 2472. It says "On start of frame reception/transmission the counter value is captured and stored into the timestamp". So that I believe "yes" in the SOF. We use STM32H753ZI however timer count is not precise value by drift of clock frequency (it seems approximately 5% difference by Logical analizer's observation). Therefore I'm concerning that "the trigger resolution" you said might be unsuitable about accuracy. In that point, may be "No".

> One probably should not use the timer overflow flag in the CAN module when using TIM3, but check directly in the timer?

I can't get point of your question exactly. So that let me describe how we use quickly, I hope that may be some help. The TIM3 is mostly used as auto-reload 16bit timer. In the case of us, we also add update event (TIM3's features) to handle wrap around and heareby are making and using stable monotonic 48bit timer for internal process.

> Is there a recommended sequence to get FDCAN time quanta and TIM3 aligned, or should we just run TIM3 with a higher frequency?

The FDCAN is only capturing counter value because of TIM3 is drived different clock source. Therefore I think just use higher frequency to keep accuracy and add post process for timestamp correction, as needed.