STM32H5 ECC errors and ICACHE invalidation

[PieterG]

Should ICACHE be invalidated when a double ECC error occurs?

[Sarra.S]

Hello @PieterG, 

Please check: How to avoid a hard fault when ICACHE is enabled on the STM32H5 series

[PieterG]

Maybe I've overlooked it, but I have read the article several times and it does not mention how ECC errors are to be handled?

I am quite sure that I read about invalidating ICACHE after a double ECC error, but I cannot find it anymore in the official documentation, nor any of the examples.

Does it make any sense to invalidate ICACHE when a double ECC error occurs in FLASH? Or is there no need for that? 

[PieterG]

@Sarra.S 

Can you please point me to where this knowledge base item explains whether ICACHE should be invalidated on double ECC errors?

Or alternatively a simple yes or no answer would also be very helpful.

[Sarra.S · Accepted solution]

Hello @PieterG, sorry for the delayed answer, 

When two ECC errors occur during a read, the flash interface sets the double error detection flag ECCD in the FLASH_ECCDETR register

and when this flag is raised, an NMI is generated, and the software must invalidate the instruction cache (CACHEINV = 1) in the NMI interrupt service routine when the ECCD flag is set.

I hope that answers your question! 

[PieterG]

Thank you @Sarra.S for your answer.

I guess invalidating the ICACHE is only necessary when ICACHE is enabled for the flash sector in which the error occurred? (in other words, I do not have to invalidate ICACHE for double ECC errors in OTP / EDATA for which I disabled caching in the MPU)

[Sarra.S]

Yes!