About PieterG

PieterG · 2024-10-24

Today, I suddenly experienced a bus fault on my stm32h563 which I traced down toDBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_IWDG_STOP;which I use to configure the watchdog to stop when the core has been halted by the debugger. fault status registers:SCB-...

PieterG · 2024-06-06

Should ICACHE be invalidated when a double ECC error occurs?

PieterG · 2024-06-06

In the FLASH_ECCDETR register, the ADDR_ECC field description contains:"The address in ADDR_ECC is relative to the flash memory area where the error occurred(user flash memory, system flash memory, data area, read-only/OTP area)."But I'm having troub...

PieterG · 2024-06-04

I'm trying to use the STM32H563 HASH peripheral to speed up sha256 calculations.The examples all use HAL_HASH_Start() to write the entire message at once.However, I'd like to feed chunks of data to the peripheral. The OEMiROT mbedtls sha256_alt drive...

PieterG · 2024-05-21

I'm trying to use CMSIS DSP on a STM32H563, but I do not get the expected results.In X-CUBE-ALGOBUILD.1.3.0, when I select DSP Library in STM32CubeMX, the installed arm_math.h does not list Cortex-M33 support: #error "Define according the used Corte...

PieterG · 2024-11-15

That is exactly what I am doing, as you can see in the SCB->BFAR value in my busfault dump: 0x44024008 What I'm doing is the same as what the __HAL_DBGMCU_FREEZE_IWDG() macro does:#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_AP...

PieterG · 2024-06-20

Thank you @Sarra.S for your answer.I guess invalidating the ICACHE is only necessary when ICACHE is enabled for the flash sector in which the error occurred? (in other words, I do not have to invalidate ICACHE for double ECC errors in OTP / EDATA for...

PieterG · 2024-06-20

Am I the only one struggling with this?Or is everyone just ignoring ECC error NMI's?

PieterG · 2024-06-20

@Sarra.S Can you please point me to where this knowledge base item explains whether ICACHE should be invalidated on double ECC errors?Or alternatively a simple yes or no answer would also be very helpful.

PieterG · 2024-06-07

Maybe I've overlooked it, but I have read the article several times and it does not mention how ECC errors are to be handled? I am quite sure that I read about invalidating ICACHE after a double ECC error, but I cannot find it anymore in the official...

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STM32H5 bus fault writing DBGMCU_APB1FZR1_DBG_IWDG_STOP

STM32H5 ECC errors and ICACHE invalidation

STM32H5 FLASH_ECCDETR address decoding

STM32H5 HASH peripheral chunk sizes

STM32H5 DSP support

Re: STM32H5 bus fault writing DBGMCU_APB1FZR1_DBG_IWDG_STOP

Re: STM32H5 ECC errors and ICACHE invalidation

Re: STM32H5 FLASH_ECCDETR address decoding

Re: STM32H5 ECC errors and ICACHE invalidation

Re: STM32H5 ECC errors and ICACHE invalidation