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Sarra.S · 2024-01-19

Introduction This article presents a quick guidance on how to prevent HardFault occurrences when the ICACHE is enabled on the STM32H5 MCU. 1. Summary and description This article explains why a HardFault may occur when accessing the following: Int...

Sarra.S · 2023-05-17

This article provides guidelines on how to use the LPBAM feature in the STM32U5 series to allow peripherals to be autonomous and optimize the power consumption in STOP2 mode.The LPBAM stands for low-power background autonomous mode. It is an operatin...

Sarra.S · 2024-07-23

did you try disabling debug in lp mode as suggested?

Sarra.S · 2024-07-23

Hello @Brigei any updates?

Sarra.S · 2024-07-23

Hello @A Maq, As described in building and using MCUBoot with Zephyr; in paragraph signing the application, "In order to upgrade to an image (or even boot it, if MCUBOOT_VALIDATE_PRIMARY_SLOT is enabled), the images must be signed. To make developm...

Sarra.S · 2024-07-19

Hello @AKova.3, Ensure that your linker script correctly defines the SRAM4 section and that it is properly mapped (you could share it) Only data/ variable used by DMA need to be defined in SRAM4, no other code parts are needed

Sarra.S · 2024-07-19

Hello @Aurelien1, One way is to use the DMA linked list to link the nodes and enable buffer chaining => check this presentation

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How to avoid a HardFault when ICACHE is enabled on the STM32H5 series

How to use the LPBAM feature: An example using STM32U5 board

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Re: Which code needs to be put in SRAM4 when using LPBAM tool

Re: STM32U545 : LPBAM cotinuous ADC multichannel