STM32G474 ADC Master-Slave

[Manu Abraham]

I am slightly confused with the ADC Master - Slave configuration. Maybe someone can shed a bit of light in here.

Using a STM32G474RET (LQFP64), thinking of chaining ADC1 and 2 in a master/slave configuration. Looking at the attached schematic, PB1 and PB2 in such a configuration, what would they be named in such an ADC setup ?

Thanks,

Manu

[Manu Abraham]

Replying to my own question, after an extensive search:

I find that PB1 and PB2 are unusable simultaneously, as they both share IN12 ?

Can someone confirm this ?

Another question that I have on the same topic:

ADC1 & 2 used in Master - Slave mode (Dual Regular Simultaneous: LL_ADC_MULTI_DUAL_REG_SIMULT)

In this case can DMA1 Channel1 be used to service ADC12 Master Slave as a combo ADC, rather than having 2 DMA channels ?

I was thinking of something like this:

   /* Set DMA transfer addresses of source and destination */

   LL_DMA_ConfigAddresses(DMA1,

               LL_DMA_CHANNEL_1,

               LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA_MULTI),

               (uint32_t)&adc_buf,

               LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

Can that work ?

There appears to be a lot of silence on the forum ..

Can someone please help ?

Thanks,

Manu

[Singh.Harjit]

You can do what you are thinking - use ADC1_IN12 on PB1 and ADC2_IN12 on PB2.

The pin naming scheme is:

Function | Instance | Channel

So, these are separate connections to different ADCs.

An example of a shared pin is: ADC12_IN14 on PB11.

Figure 84 to 88 in RM0440, Rev 4 are a handy reference.