N-pulse waveform generation application example - part2 (AN4776)

[M N]

Hi .

I have problem with this back to back timer configuration . (in AN4776)

What I get :

1- Timer 1 is making PWM ( i just need a regular pwm but this examle is a complementary one )

2-Timer 1 will send a trigger to timer2( which is it's controller acutlly) that I can't get how and when it will send to Timer 2.

3- Timer 2 will make a big pulse as much as all pulse we need in timer1 output PWM and after On time of this big pulse has finished in some way pwm generator (Timer 1) will stop (I don't know how)

4- Timer 2 which is controller actully will stop somehow ! AN4776 said it will stop because it is in reset mode ! ( am I right ?)( as I know slave reset mode just reinitialize values won't stop them or clear them )

So my problems is:

What is happening here .pls i got a headache at this part .

who is controlling who ? how ?! how pwm generator will stop how it will cause to stop controller timer .

[waclawek.jan]

I so far acknowledged the existence of the "timer cookbook" but honestly did not go through it. Now I read the given chapter, went through the attached code, downloaded the "Applicative [sic] examples" https://my.st.com/content/my_st_com/en/products/embedded-software/mcu-mpu-embedded-software/stm32-embedded-software/stm32cube-expansion-packages/x-cube-timcooker.html , went through the ONESHOT_COMPLYMENTARY_NPULSES_GENERATION [sic] leg of NpulseWave_TIM_Sync example, and I decided that I won't comment.

So, if you want to achieve something with the timers, read the timers chapter in RM, make some simple experiments on your own, and if you have some particular waveform in mind, come back with a fresh post and a drawing of that waveform.

JW

[M N]

Thank you ,I didn't know there is example (I looked for example in my repository folder of cubeMX but I couldn't find )​

I'll examine this example and I will back here if I'll have any question .( because I don't want a ready to use code I want to understand this example)

The point is :I usually look for RM and other notes and I had not any problem with any part of stm32 peripheral and It's for about six year I'm work in this way, but this part of this cookbook ...​..! or maybe It's my misunderstanding of RM timer part which leads me to get confused in this example.

[waclawek.jan]

As far as I can judge, this example is not intended to provide repetitive N-pulse pattern, but only one-off.

There are two methods implemented to "stop" TIM1 to output pulses, see the interrupt. The interrupts get fired when (as TIM1_DIER is set for the COMmutation event, which comes from TRGI due to TIM1_CR2.CCUS being set) DISABLING_CHANNELS_OUTPUTS simply disables both TIM1_CH1 and TIM1_CH1N using respective bits in CCER, which effectively threestates the pins in GPIO and as they have pulldown switched on (contrary to what AN4776 says) they will relatively slowly drift both to zero. SET_CHANNEL_TO_INACTIVE_STATE changes the mode to FORCED INACTIVE.

Due to TIM1_CR2.CCPC/CCUS being set, both these mechanisms get active only after a second second trigger from TRGI comes - the first one comes immediately after enabling TIM1 through the double-master-slave arrangement.

None of them stops TIM1, just disables it from outputting pulses. You can observe that in in debugger.

The master-slave connection from TIM1 to TIM2 is supposed to restart TIM2 (which was set up and enabled sooner than TIM1) as consequence of setting TIM1_UG.EGR in TIM1's startup code.

The master-slave connection from TIM2 to TIM1 is supposed to... well I'm not sure... both start TIM1 (but it's started explicitly from code, too, by setting CR1.CEN), trigger the TIM1 interrupt, and also provide the Commutation event for the CCMR/CCE preload to be loaded to the "live" registers.

The whole arrangement probably could be designed cleaner.

JW

[M N]

Thank you .

Now there are some question here .

We will disable output compare of pwm generator in ISR so do we have latency to shut it down ? ( how much it take time to turn output off (or disable it ) is it immediately or it will produce some extra unwanted pulse to output?) ( as you said "relatively slowly drift both to zero" so you mean it will produce unwanted pulse to output ?) ( I think it's related to output clock frequency and mine is about 100 khz which I'm using for driving stepper motor).

At this time above question is more important than others for me .

[M N]

Another question here is:

In previous example we will go to ISR to turn output off (disable it ) so why just we don't use One Pulse Mode timer and repetition counter register ( and because my MCU is STM32f469 so I have 8 bit repetition counter register maximum 256 time ,so It leads to problem for me because my desired output pulse is more bigger than 256 ) and setting Interrupt at the end of repetition counter register and put new value to repetition counter register and start it again ( for pulse bigger than 256 ) and repeating this procedure to produce enough pulse in output ( for example when we want about 9000 pulse to output .

will this way make problem ? my output clock is 100khz how much time ISR and putting new value to "repetition counter register" and start timer again will take time do you know ?

[waclawek.jan]

> We will disable output compare of pwm generator in ISR so do we have latency to shut it down ?

While I attempted to explain what the published code does, I also said I am not going to comment on it, I believe you understand what does that mean.

I am not entirely sure but if it works as I imagine it may employ the preloaded values for either CCER or CCMR, depending on the selected #define. Those would then became active upon trigger/commutation, i.e. independent on the inetrrupt latency.

However, what I wrote above about "drifting to zero" applies to the case when the output channels are disabled by clearing (preloaded) enable bits in CCER. That means that, in default setting of things, the output transistors on the pins are disengaged, and only the pullup set in the GPIO setup is pulling the pins low. Then it depends on the parasitic capacitances loading those pins, how long this takes. Note, that if the pin's state was low at the moment of switchoff (which depends on particular polarities' settings and the deadtime), then it remains low, pulled low weakly by the pulldown (unless there's any external pullup source).

The other #define setting, i.e. setting the channel to some of the Forced state in CCMR, leaves both the direct and negated channel driven to level given by that Forced state, plus any polarity setting in CCER.

Now go to Output control bits for complementary OCx and OCxN channels with break feature table in RM and notice the lines where MOE=1, OSSR=1 and some of CCxE/CCxNE is 0 - by disabling only one of the channels in CCER, and forcing a particular level of OCxRef, you may be able to actively drive both channels to whatever level you want.

> much time ISR and putting new value to "repetition counter register" and start timer again will take time

The problem with ISR is, that there are many factors which come into calculating latencies - other interrupts with the same or higher priority, latency due to multicycle instructions, FLASH latency, bus contention, etc. etc.

OTOH, TIMx_RCR is preloaded, too; it means, that as soon as you start a RCR cycle, you can immediately rewrite the RCR value, and that will become "active" when the current RCR cycle ends.

JW