Stm32G431KBU6 CANFD can't work when BRS On？

[eason_Yi]

Hi community：

     I'm using CANFD on stm32g431kbu6 board, but I find some issue that CANFD cant work normally with BRS ON，my config of CANFD show in the comments。Does anyone know about this？

Thanks

[eason_Yi]

[mƎALLEm]

Hello and welcome to the community.

First, please see these guidelines when posting:

https://community.st.com/t5/community-guidelines/how-to-write-your-question-to-maximize-your-chances-to-find-a/ta-p/575228

Second, as stated in the guidelines above, you need to provide more information.

1. What do you mean by "cant work normally"? no transmit? no receive? sometimes work sometimes not? please be concise.
2. Did you test your solution in Loopback mode?
3. Please provide details about your HW? which board? ST board? custom board? how about the transceiver? which transceiver part number?
4. Please provide details about your CAN bus config? what is connected to?
5. What about the clock source you're using? HSE/HSI?
6. What about the filter config?

Need also to share your project, schematics if possible. Hard to tell about your issue based on the few lines you posted.

[eason_Yi]

OK, and I find the reason, there is another CAN node with inconsistent data area sampling points （80%）in my CAN bus，my setting is 75%,so when it work together, CAN bus hang up

[mƎALLEm]

Hello,

Thank you for the feedback. But I'm not sure the issue is related to the sampling point. 80% or 75% as sampling points position don't make a difference, it could be something else .. May be it's a resolution of the bit time issue based on time quanta of that another CAN node.

[eason_Yi]

Thanks for your reply，
I will keep on troubleshooting this issue. And I wanna know if the FDCAN of Stm32G431KBU6 can automatically recovery from bus-off status to error-active state？if yes, should i set some register bits to enable this feature like CAN_MCR:ABOM of Stm32f103 series？I did not find any register about this in RM0440 Reference manual

[mƎALLEm]

Hello,

You need to open a new thread for this new question.

Thank you for your understanding :).

[eason_Yi]

I find some issues in different config of  FDCAN,

my configs list below:

PCLK of FDCAN is 160MHz

Data Prescaler：8

Data Sync Jump Width: 1

Data Time Seg1:2

Data Time Seg2:1

When I config like this, I saw that the TEC keep increasing until the CAN controller enters bus-off status， then DLEC changes from 0x100（Bit Error） to 0x111

But if I make some change，it works well, configs list below:

PCLK of FDCAN is 160MHz

Data Prescaler：4

Data Sync Jump Width: 1

Data Time Seg1:5

Data Time Seg2:2

So whats the minimal value of Data Time Seg1 and Data Time Seg2?

[eason_Yi]

OK, I'll open a new one later, Thanks

[mƎALLEm]

---

@eason_Yi wrote:

I find some issues in different config of  FDCAN,

my configs list below:

PCLK of FDCAN is 160MHz

Data Prescaler：8

Data Sync Jump Width: 1

Data Time Seg1:2

Data Time Seg2:1

When I config like this, I saw that the TEC keep increasing until the CAN controller enters bus-off status， then DLEC changes from 0x100（Bit Error） to 0x111

But if I make some change，it works well, configs list below:

PCLK of FDCAN is 160MHz

Data Prescaler：4

Data Sync Jump Width: 1

Data Time Seg1:5

Data Time Seg2:2

So whats the minimal value of Data Time Seg1 and Data Time Seg2?

---

But this is not the values you shared in your first comment.. Otherwise I did suggest you to change this.