Hi ;
I'm trying to configure the ADC1 and ADC2 modules to get them triggered via tim1_trgo2 for a dual simultaneous regular conversion start but no success until now .
Before I tried to do this I verified that I can succesfully trigger these modules over a software trigger using the master module's 'ADSTART' bit and get the results .
Here is the configuration scheme ;
ADC1 is configured to convert only 1 channel (ADC1_IN1) , ADC2 is also configured to convert one channel (ADC2_IN2) , both channels 'Regular channel sequence length' is set to 0 , and as known both channels are a fast ADC channel not one of those slow ones so the conversion durations are equal
Both channel is configured to convert at hardware oversampler mode , 128 conversions and shifting the result by 7 , ROVSE is enabled.
ADC clock is selected as 'System clock selected as ADC1/2 clock' from the RCC_CCIPR . ADC_CCR , CKMODE is set to '00' (Asynchronous Clock Mode) and the prescaler is et to 6 using ADC_CCR_PRESC bits.
According to the scheme I explained above everything works fine using ADSTART bit of the master .
But when I add the code
EXTSEL = 10 (tim1_trgo2 is interconnected on the line '10' for ADC1/2 Regular Conversions),
EXTEN=1 (Rising edge) to both ADC1 and ADC2
with
TIM1 , CR2 , MMS2= [0010]
Update - the update event is selected as trigger output (tim_trgo2). For instance, a
master timer can then be used as a prescaler for a slave timer.
My ADC modules don't get triggered at all ... I almost read the entire datasheet with the ERRATA sheet but can't find a way to make it work . Timer is also enabled and periodic timer interrupt is observed via a scope on a pin toggle. (So we know that an update event occurs)
A help would be so appreciated.
