Back to back reads of RTC registers sometimes show increasing SubSeconds

[matkSENS]

I think I may have found a bug with the STM32G4 RTC that I am not seeing in the errata.

I am using the RTC on STM32G4 with a 32.768 KHz LSE oscillator. I am having a issue where I would read the RTC twice fairly close together in code. I observed that occasionally on the 2nd read of the RTC the SSR value would increase without a change to either the TR or DR. I tested with shadow bypass both enabled and disable and I observed the same behavior.

I tried to profile the SSR values that I would get which triggered this condition and I noticed that the 2nd read was often 3 more than the 1st read (ex. 22492 and 22495) but sometimes the 2nd read was even more. It also seemed that multiple least significate bits of the 1st read were 0; I suspect that this could be explained by the fact the RTC is not on the same clock domain and I happen to be reading the SSR in the middle of a decrement before the bits are stable.

I seem to be able to work around this by reading the RTC registers 2 times until they match. I saw this is needed on older processors with a RTC shadow register bug.

Is this a known issue, a new issue, or am I doing something wrong?

[Andrew Neil · Accepted solution]

I think this is a known issue:

https://community.st.com/t5/stm32-mcus-products/stm32f4-stm32h7-rtc-hw-bug-shadow-registers-for-seconds-and/td-p/102958/page/2

http://efton.sk/STM32/gotcha/g95.html

[matkSENS]

Thanks! Those do seem to be the same issue. It almost seems like shadow RTC registers just don't work. I was surprised that "bits within registers were inconsistent" but I could not find that documented in the G4 RM. It makes sense why as they are in different clock domains. Reading the registers twice until the values are consistent seems to be the best way to go.

[waclawek.jan]

As I wrote in the article @Andrew Neil linked to above, I've observed this only when BYPSHAD=1. I would be surprised to see it when BYPSHAD=0 as one of the purposes of the shadow registers readout mechanism is exactly to eliminate problems stemming from reading asynchronously clocked counters (the other is to provide consistent readout of multiple registers i.e. SSR+TR+DR through the locking mechanism).

Btw. 'G4 has RTCv3, which does not suffer from the "sometimes shadow registers won't lock" erratum.

JW