STM32F407 What is normal ADC accuracy error?

[LPetr.1]

Hello. I have an external circuitry that I want to monitor voltage. It can go up to 48V hence I have used a big voltage divider. I am using 220K and 10K resistors for my voltage divider.

At the moment, I am measuring 24V external voltage. After the voltage divider, the voltage is: 1.030V (Measured with multimeter), according to the voltage divider formula, it should be 1.043V but that slight deviation is probably due to the accuracy of the resistors.

If I see 1.030V on the pin using the multimeter, the measured voltage should be 23.69V but the actual voltage that my STM32 is measuring on the ADC pin is 23.3V which is quite a bit off. Is this a normal ADC error for the STM32 or I am doing something wrong?

Is there any way to achieve slightly better accuracy? I dont want to hardcode the offset value as I am not certain it will be the same for other devices.

[Simon V.]

Hello,

Measuring ADC input voltage with high impedance value is requiring a long sampling time. You can refer to AN2834 which describes the ADC sampling time constraints.

Do you observe the same voltage offset with the ADC sampling time configuration at the maximum value ? SMPx = 111 <-> 480 cycles.

It is also possible to reduce the frequency of the ADC @ 1MHz to increase the sampling time.

Let me know if it helps you.

Regards,

Simon

[LPetr.1]

Thank you for response:

I have set the ADC sampling time to 480 and I can see that it is more accurate already. Just to clarify:

My clocks are configured as following:

 

As you can see, the APB peripheral clock is set to 84Mhz.

I have configured the ADC sampling time to be 480 cycles. I am using 9 channels for ADC. Does that mean that in order for all 9 channels to finish DMA conversion it will take 480*9 = 4320 cycles.

If one peripheral clock is 0.0119 micro seconds ( 1/84Mhz), does that mean that all 9 channels will complete the DMA conversion in 0.0119*4320 = 51.408 micro seconds?

Is my calculation correct?

[Simon V.]

Hello,

Yes but you must also include the conversion time which is 12 cycles per acquisition.

If ADC acquisition is in 9 channel in serial then DMA conversion time = (1/84MHz) x 9 x (480 +12) = 52.71us

At each channel acquisition, DMA transfert is done in parallel, expected for the last one...so extra cost is about couples of bus clock cycles...

Again, depending on your application, you can reduce the FADC to increase the sampling time to fit your application accuracy requirement.

Regards,

Simon