Beginning to explore timers in STM32F051 (from DiscoveryF0). I'm starting with TIM6 (basic timer) as I'm looking for nothing more than a periodic interrupt. Before I get started, I'm wrestling with where to find complete register reference for the component (I plan to interact with timers at register level, bit-by-bit, to learn in detail.)
Datasheet for STM32F051 says
3.14.3 Basic timer TIM6
This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit time base.
(I'm not concerned about DAC trigger, just wanted a generic timer.)
RM0091 Section 21,Table76 page 559 defines 8 registers as follows (offsets and names shown below)
0x00 TIMx_CR1
0x04 TIMx_CR2
0x0C TIMx_DIER
0x10 TIMx_SR
0x14 TIMx_EGR
0x24 TIMx_CNT
0x28 TIMx_PSC
0x2C TIMx_ARR
STM32F051x8.h (in Drivers/CMSIS/Device/ST/STM32F0xx/Include/) defines the register structure for TIM6 using a template (TIM_TypeDef) that appears to be common to many (most? all?) timers, which is why I'm asking my question:
(line 591 of STM32F051x8.h)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
This refers to a structure definition containing 21 register offsets, not 8.
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
} TIM_TypeDef;
To get a complete picture of operating TIM6, should I refer to other timers' definitions for the registers which are not defined in the TIM6 section of RM0091 (section 21) - that is, not rely solely on the definition in section 21?
Is the idea that TIM_TypeDef is common and then each individual timer customizes from there? Does TIM6 incorporate the full register set in TIM_TypeDef?
Thanks for any clarification!
