STM32F030CC 48MHz PLL and SysTick...What am I missing?

[Tim_24]

Hi,

I'm trying to set the PLL output to 48MHz on a STM32F030CC:

HSI = 8MHz

RCC->CFGR PLLSRC = 0 (PLL input = HSI/2),

PREDIV = not divided.

PLLMUL = 12;

should give (8MHz/2) * 12 = 48MHz but instead I get no clock output on MCO.

Using the MCO output I have confirm the HSI is running, other multiplier factors work fine - I've tried PLLMUL = 10 for example - I would expect (8MHz/2)*10 = 40MHz then MCO divides this by 2 onto the output and I read 20MHz using my scope...works perfectly but not PLLMUL = 12 just a flat line on my scope and no code runs.

If I run the code with the debugger (ST-Link V2, SWDIO/SWCLK connections) it seems to run fine unless I have SysTick interrupt enabled...

Something odd going on, hopefully someone can point me in the right direction?

Thanks,

Tim

[Tim_24]

Update on this - It works fine (48MHz PLL) providing HCLK is divided by 4 (RCC_CFGR_HPRE_DIV4) anything less (div by 2/no div) and the code doesn't run.

Is there a limitation to the HCLK speed I am not aware of? The Reference Manual (RM0360) says "The AHB and APB domains maximum frequency is 48MHz" so I should have no problem to set HCLK/PCLK to no div but this is not the case?

Thanks,

Tim

[waclawek.jan]

If you apply PLL output to HCLK, do you change FLASH latency accordingly?

JW

[Tim_24]

Flash latency set to 1.

Strangely I've tested the same code on other STM32 out of the same 'family' (STM32F030RC, STM32F030R8, STM32F030C8) and not come across the issue - only STM32F030CC.

For now I have HCLK set at DIV4 and PCLK set at no div, then adjusted my timers/SysTick etc.

Tim