2024-10-28 01:44 AM
Trying to write a i2c driver for the stm32f0 and having trouble understanding how this works as im use to the stm32f4 i2c could anyone describe what steps i need to take to write a polling i2c driver or point me to an app note that describes ive ben reading the reference manual and just scratching my head lol
2024-10-28 02:05 AM
Hi @Franksterb92 ,
You can refer to the I2C examples provided in STM32SnippetsF0 package.
To know more about this package and how to run the examples, you can refer to https://www.st.com/resource/en/data_brief/stm32snippetsf0.pdf.
-Amel
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2024-10-28 04:22 AM
And why don't you study the HAL source code?
2024-10-28 04:29 AM
and/or the Standard Peripheral Library (SPL) code:
https://www.st.com/en/embedded-software/stsw-stm32048.html
2024-10-28 12:14 PM
i am but some of it to me i have to look at for a good while to understand whats going on as with hal there are so much that you can configure
2024-10-28 12:45 PM
one of my biggest questions is. in the cr2 register does the RD_WRN bit handle the 0 or 1 of the slave address to tell the slave if its a read or write so example if i want to read from slave i just send the 7 bit address say its 0x53 to SADD register and set RD_WRN to 1 and the Hardware changes it to 0xA7 or do i still need to alter the SADD to achieve this
2024-10-28 01:00 PM - edited 2024-10-28 01:01 PM
The 'F0 and later STM32 families' I2C is very different from the 'F1/'L1/'F2/'F4.
In other words, if the 7-bit address is 0x53, you write 0xA6 into SADD field, and yes, 0 or 1 to RD_WRN.
Try. You don't need to write any program, just enable it in RCC, write any reasonable value into TIMINGR, then in debugger set I2C_CR1.PE (clearing it always resets the I2C), and then experiment with writing into CR2 and DR, and reading the ISR. Use a LA to observe what happens at SDA/SCL. Should be fun, until you get to the pesky details.
JW
2024-10-28 01:10 PM
so that rd_wrn does not alter the sadd by hardware i have to do that myself
2024-10-28 02:36 PM
Why would RD_WRN alter SADD?
What matters is, what is transmitted on SDA/SCL. And there, the last bit of first byte is the content of RD_WRN.
JW
2024-10-30 10:44 PM
i wasn't sure why that bit even exist just thought maybe the hardware would change the slave address so you wouldn't have to in code the reference manual isn't so clear