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STM32F0 Bare Metal I2C

Franksterb92
Senior

Trying to write a i2c driver for the stm32f0 and having trouble understanding how this works as im use to the stm32f4 i2c could anyone describe what steps i need to take to write a polling i2c driver or point me to an app note that describes ive ben reading the reference manual and just scratching my head lol

9 REPLIES 9
Amel NASRI
ST Employee

Hi @Franksterb92 ,

You can refer to the I2C examples provided in STM32SnippetsF0 package.

To know more about this package and how to run the examples, you can refer to https://www.st.com/resource/en/data_brief/stm32snippetsf0.pdf.

-Amel

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

gbm
Lead III

And why don't you study the HAL source code?

My STM32 stuff on github - compact USB device stack and more: https://github.com/gbm-ii/gbmUSBdevice

and/or the Standard Peripheral Library (SPL) code:

https://www.st.com/en/embedded-software/stsw-stm32048.html

 

i am but some of it to me i have to look at for a good while to understand whats going on as with hal there are so much that you can configure 

Franksterb92
Senior

one of my biggest questions is. in the cr2 register does the RD_WRN bit handle the 0 or 1  of the slave address to tell the slave if its a read or write so example if i want to read from slave i just send the 7 bit address say its 0x53 to SADD register and set RD_WRN to 1 and the Hardware changes it to  0xA7 or do i still need to alter the SADD to achieve this 

The 'F0 and later STM32 families' I2C is very different from the 'F1/'L1/'F2/'F4.

waclawekjan_0-1730145423314.png

In other words, if the 7-bit address is 0x53, you write 0xA6 into SADD field, and yes, 0 or 1 to RD_WRN.

Try. You don't need to write any program, just enable it in RCC, write any reasonable value into TIMINGR, then in debugger set I2C_CR1.PE (clearing it always resets the I2C), and then experiment with writing into CR2 and DR, and reading the ISR. Use a LA to observe what happens at SDA/SCL. Should be fun, until you get to the pesky details.

JW

so that rd_wrn does not alter the sadd by hardware i have to do that myself 

Why would RD_WRN alter SADD?

What matters is, what is transmitted on SDA/SCL. And there, the last bit of first byte is the content of RD_WRN.

JW

i wasn't sure why that bit even exist just thought maybe the hardware would change the slave address so you wouldn't have to in code the reference manual isn't so clear