STM32 U575 LSE Clock doesn't start.
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‎2022-09-16 3:10 AM
LSE clock is set in the Cube and initialised
After intitialisation the following registers are not set correctly and the LSE clock isn't called
RCC->BDCR->LSEDRIVE not set to hight event though macro called
RCC->BDCR->LSCOSEL set to LSI
RCC->BDCR->LSCOEN not set
This looks to be a bug in the HAL library
Solved! Go to Solution.
- Labels:
-
RCC
-
STM32U5 series
Accepted Solutions
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‎2022-09-16 7:18 AM
I found the problem
I was calling __HAL_RCC_PWR_CLK_ENABLE();
Before SystemClock_Config which was why the __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)
Didn’t work.
All fixed now
Kind regards
Sue
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‎2022-09-16 3:34 AM
Hello,
If you can, please share the.ioc file as you are using CubeMX or IDE, or share some code, so that the community can check/reproduce/help.
Does this happen on a nucleo board ?
>> This looks to be a bug in the HAL library
That can happen, but we need more inputs.
Thank you.
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‎2022-09-16 3:51 AM
Yes this happens on a nucleo board as well
Have attached project
Sue
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‎2022-09-16 5:21 AM
I managed to get the LSE clock running by adding this code
/* USER CODE BEGIN SysInit */
// re-jig the LSE clock
// STOP LSE clock
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
SET_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL);
SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
/* USER CODE END SysInit */
Sue
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‎2022-09-16 7:18 AM
I found the problem
I was calling __HAL_RCC_PWR_CLK_ENABLE();
Before SystemClock_Config which was why the __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)
Didn’t work.
All fixed now
Kind regards
Sue
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‎2022-09-19 6:11 AM
> I was calling __HAL_RCC_PWR_CLK_ENABLE();
> Before SystemClock_Config which was why the
> __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)
> Didn’t work.
I fail to see the causality here.
JW
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‎2022-09-23 1:25 AM
Enabled the LSE clock so that the call to __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)
Didn’t work as the clock was enabled and the calls can only work if disabled.
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‎2022-09-26 4:07 PM
Enabling the clock for PWR peripheral has nothing to do with RCC_BDCR register, in which the LSE is configured.
