cancel
Showing results for 
Search instead for 
Did you mean: 

STM32 U575 LSE Clock doesn't start.

sneal
Associate II

LSE clock is set in the Cube and initialised

After intitialisation the following registers are not set correctly and the LSE clock isn't called

RCC->BDCR->LSEDRIVE not set to hight event though macro called

RCC->BDCR->LSCOSEL set to LSI

RCC->BDCR->LSCOEN not set

This looks to be a bug in the HAL library

1 ACCEPTED SOLUTION

Accepted Solutions
Hi Mike,
I found the problem
I was calling __HAL_RCC_PWR_CLK_ENABLE();
Before SystemClock_Config which was why the __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)
Didn’t work.
All fixed now
Kind regards
Sue

View solution in original post

7 REPLIES 7
Mike_ST
ST Employee

Hello,

If you can, please share the.ioc file as you are using CubeMX or IDE, or share some code, so that the community can check/reproduce/help.

Does this happen on a nucleo board ?

>> This looks to be a bug in the HAL library

That can happen, but we need more inputs.

Thank you.

Hello,
Yes this happens on a nucleo board as well
Have attached project
Sue
HI Mike,
I managed to get the LSE clock running by adding this code
/* USER CODE BEGIN SysInit */
// re-jig the LSE clock
// STOP LSE clock
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);
SET_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL);
SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
/* USER CODE END SysInit */
Sue
Hi Mike,
I found the problem
I was calling __HAL_RCC_PWR_CLK_ENABLE();
Before SystemClock_Config which was why the __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)
Didn’t work.
All fixed now
Kind regards
Sue

> I was calling __HAL_RCC_PWR_CLK_ENABLE();

> Before SystemClock_Config which was why the

> __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)

> Didn’t work.

I fail to see the causality here.

JW

__HAL_RCC_PWR_CLK_ENABLE()
Enabled the LSE clock so that the call to __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)
Didn’t work as the clock was enabled and the calls can only work if disabled.

Enabling the clock for PWR peripheral has nothing to do with RCC_BDCR register, in which the LSE is configured.