SPI interface between Nucleo-STM32L476RG and TI CC1200. 1. How to adjust to adjust SCK/Baudrate? 2. How to adjust interval between NSS/CSN state change and start/stop of SCK pulse?

[EMarv.1]

I have set up an SPI interface between Nucleo-STM32L476RG and TI CC1200. Working in STMCube IDE and mostly using MX to generate drivers for SPI2. The SPI interface works and I am able to send comands and receive regster values to/from CC1200 however, I am unable to change the SCK rate (stays at 3.846Mhz) even though I have raised and lowered hspi2.Init.BaudRatePrescaler = SPI_BAUDRATE. HCLK=80Mhz PCLK1 and 2= 80 Mhz. Maybe something else I need to set? The goal is 10Mhz Baudrate. Also there is a ~4us delay from start of low state on CSN (start of transaction) to Start of SCK pulses and an ~8us delay from last SCK pulse to CSN state=high (end of transaction). I have tried disabling NSS and set GPIO to toggle "manually" before and after calling HSPI2 TX RX function but the CSN-SCK dalay was the same. I also tested the SPI interface with an MSP430 and the CSN-SCK delay was ~710ns. I am fairly new to STM32 so I'm sure what to check next in code. Any ideas? The goal here is to make the transaction as fast as possible within the 10Mhz constraints of the CC1200.

//See SPI Init below:

static void MX_SPI2_Init(void)

{

 /* USER CODE BEGIN SPI2_Init 0 */

 /* USER CODE END SPI2_Init 0 */

 /* USER CODE BEGIN SPI2_Init 1 */

 /* USER CODE END SPI2_Init 1 */

 /* SPI2 parameter configuration*/

 hspi2.Instance = SPI2;

 hspi2.Init.Mode = SPI_MODE_MASTER;

 hspi2.Init.Direction = SPI_DIRECTION_2LINES;

 hspi2.Init.DataSize = SPI_DATASIZE_8BIT;

 hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;

 hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;

 hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT;

 hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;

 hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;

 hspi2.Init.TIMode = SPI_TIMODE_DISABLE;

 hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;

 hspi2.Init.CRCPolynomial = 7;

 hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;

 hspi2.Init.NSSPMode = SPI_NSS_PULSE_DISABLE;

 if (HAL_SPI_Init(&hspi2) != HAL_OK)

 {

  Error_Handler();

 }

 /* USER CODE BEGIN SPI2_Init 2 */

 /* USER CODE END SPI2_Init 2 */

}

STM32-CC1200 at 3.846Mhz

MSP430-CC1200 at 12.5Mhz

 

[MM..1]

Seems your clock config is bad try show sending code part too.

[EMarv.1]

Thank you for your response. Any thoughts on what area of clock config to look at?

By "show sending code did you mean HSPI2 TX RX like:

buffer_tx[1]=0;

  for (i=128;i < 176;i++)

  {

  buffer_tx[0]=i;

  printf("\r\nPrint TX Buff : %X", buffer_tx[0]-128);

  HAL_SPI_TransmitReceive_IT(&hspi2, buffer_tx, buffer_tx, 2);

  HAL_Delay(1000);

  printf("\r\nPrint CC1200 Reg Buff : ");

  int j;

for (j=0;j < (sizeof (buffer_rx) /sizeof (buffer_rx[0]));j++)

{

 printf(",%X ",buffer_rx[j]);

}

  printf("\n ");

  }

[waclawek.jan]

> I am unable to change the SCK rate (stays at 3.846Mhz) even though I have raised and lowered

> hspi2.Init.BaudRatePrescaler = SPI_BAUDRATE. HCLK=80Mhz PCLK1 and 2= 80 Mhz.

80MHz/3.846MHz=cca 20 and there is no such divider. You haven't shown us the B-D measurement on the above picture, but to me it looks more like 1.6us which means 5MHz SCK rate, that would be the more sane divider of 16.

Single-step through the code and observe what's written into SPIx_CR1.BR. Now change the divider in your code and do the same and compare.

> I have tried disabling NSS and set GPIO to toggle "manually" before and after calling HSPI2 TX RX function but the CSN-SCK dalay was the same. I

You did not show us how do you do that.

JW

[EMarv.1]

OK. I figured out the main issue was I had copied the Blinky project and renamed for further work on this project. Somehow the blinky.ioc and main.c were still being used even though eclipse said it was building and debugging the new project. I guess I need to learn how to clone projects properly. Also the SPI-SCK rate was at 5Mhz once I measured properly and this makes much more sense since the old Blinky.ioc was /16. NSS-SCK interval is now short as expected when using NSS mode instead of manual IO. Speed is now 10Mhz. Only problem is I need to get rid of the NSS pulse between bytes. The CC1200 needs a steady low state on CSN throughout the transaction. Any thoughts?