About EMarv.1

EMarv.1 · 2022-02-02

Interface of STM32L476RG to TI CC1200 SPI. Using MCU registers with NSS produces short acceptable CSN to clock start interval but I cannot get rid of the high pulse between frames which causes the CC1200 to malfunction. Manually configuring and toggl...

EMarv.1 · 2022-01-26

I have set up an SPI interface between Nucleo-STM32L476RG and TI CC1200. Working in STMCube IDE and mostly using MX to generate drivers for SPI2. The SPI interface works and I am able to send comands and receive regster values to/from CC1200 however,...

EMarv.1 · 2022-02-06

Much appreciated. The links you provided in your answer have helped me avoid the pitfalls mentioned. based on some initial testing/mod of HAL SPI driver, it looks like using manual GPIO and optimizing start of CS low is not much of an issue for trans...

EMarv.1 · 2022-02-06

Thank you for confirming. Just trying to avoid custom code where possible and appreciate you confirming that there was not a trick I could use to make HAL driver function the way CC1200 needs no NSSP CS and short. You're right, normally I would not b...

EMarv.1 · 2022-02-02

Just to be clear, I think you are saying that whether I use code within the SPI_transmit_receive function to manually config and toggle the CS GPIO or enable/disable the peripheral- the interval between CS low/high and clock pulse start/stop will lik...

EMarv.1 · 2022-02-02

> CS is low as long as the peripheral is enabled (not at long as it's active).Interesting that when NSSP is enabled CS goes low within a few hundred nanoseconds of clock pulse start. Yet, the peripheral is enabled long before that. Oh, maybe what you...

EMarv.1 · 2022-01-27

OK. I figured out the main issue was I had copied the Blinky project and renamed for further work on this project. Somehow the blinky.ioc and main.c were still being used even though eclipse said it was building and debugging the new project. I guess...

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Is there a way to make SPI NSS hardware output produce a steady state low without NSSP during SPI transaction without manual config and toggle of CSN GPIO?

SPI interface between Nucleo-STM32L476RG and TI CC1200. 1. How to adjust to adjust SCK/Baudrate? 2. How to adjust interval between NSS/CSN state change and start/stop of SCK pulse?

Re: Is there a way to make SPI NSS hardware output produce a steady state low without NSSP during SPI transaction without manual config and toggle of CSN GPIO?

Re: Is there a way to make SPI NSS hardware output produce a steady state low without NSSP during SPI transaction without manual config and toggle of CSN GPIO?

Re: Is there a way to make SPI NSS hardware output produce a steady state low without NSSP during SPI transaction without manual config and toggle of CSN GPIO?

Re: Is there a way to make SPI NSS hardware output produce a steady state low without NSSP during SPI transaction without manual config and toggle of CSN GPIO?

Re: SPI interface between Nucleo-STM32L476RG and TI CC1200. 1. How to adjust to adjust SCK/Baudrate? 2. How to adjust interval between NSS/CSN state change and start/stop of SCK pulse?