2024-07-04 12:38 AM - edited 2024-07-04 01:22 AM
hi
1. STM32F722ZE & Winbond SDRAM is working fine with follow setting .
W9825G6KH-6I 166MHz/CL3 or 133MHz/CL2
CASLatency = FMC_SDRAM_CAS_LATENCY_3;
SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3;
my understanding was MCU main clock was divide by 2 is made on below .
Initially i kept the SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; but it's not working then i changed to SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3; and then it's started working .
i). what is exact speed now SDRAM is working 108Mhz or 72Mhz ?.
ii). Initially i calculated the timing by 216Mhz/2 = 108Mhz = 9.26ns . should i need change the timing according to 72Mhz .??
iii) what is role of 166MHz/CL3 or 133MHz/CL2 ??.
2. SDRAM is working perfectly by HAL_SDRAM _read.
How to handle SDRAM by DMA access specifically DMA _Read .
#define SDRAM_ADD_1 0xC0000000
#define SDRAM_ADD_2 0xC0000060
i). i enabled the DMA mem to mem with word (source and destination )and then started DMA by below .
HAL_DMA_Start(&hdma_memtomem_dma2_stream0, (uint32_t)SDRAM_ADD_1, (uint32_t)rdata,10);
HAL_DMA_Start(&hdma_memtomem_dma2_stream1, (uint32_t)SDRAM_ADD_2, (uint32_t)rdata,10);
accessed DMA by
HAL_SDRAM_Read_DMA(&hsdram1, (uint32_t*)SDRAM_ADD_1, (uint32_t*)rdata, 10);
HAL_Delay(1000);
HAL_SDRAM_Read_DMA(&hsdram1, (uint32_t*)SDRAM_ADD_2, (uint32_t*)rdata, 10);
but stream0 is not working from address 1
stream1 is not working from address 2 .
i need access the SDRAM address randomly , so i need change the HAL_DMA_Start every time ?.
i think i am not approaching DMA properly . please suggest me how to approach SDRAM - DMA_Read with random address access
Solved! Go to Solution.
2024-09-07 06:15 AM - edited 2024-09-07 07:12 AM
Hello,
Not sure what the problem is and what do you mean by
@MMARI.1 wrote:
but stream0 is not working from address 1
stream1 is not working from address 2 .
The data written is not read back correctly?
But from this statement, I understand you can read the SDRAM using the CPU but not with DMA but you didn't mention what the problem is? uncorrect data? always 0? or what?
@MMARI.1 wrote:
2. SDRAM is working perfectly by HAL_SDRAM _read.
How to handle SDRAM by DMA access specifically DMA _Read .
#define SDRAM_ADD_1 0xC0000000 #define SDRAM_ADD_2 0xC0000060
To me, if you are reading perfectly the data by writing and reading them back using the CPU it deas mean your FMC config is good.
Now I'm wondering if you are taking care of the cache coherency as you are transferring the data and reading them back using the CPU! refer to the AN4839 Level 1 cache on STM32F7 Series and STM32H7 Series/ 3.2 Example for cache maintenance and data coherency
2024-09-07 06:15 AM - edited 2024-09-07 07:12 AM
Hello,
Not sure what the problem is and what do you mean by
@MMARI.1 wrote:
but stream0 is not working from address 1
stream1 is not working from address 2 .
The data written is not read back correctly?
But from this statement, I understand you can read the SDRAM using the CPU but not with DMA but you didn't mention what the problem is? uncorrect data? always 0? or what?
@MMARI.1 wrote:
2. SDRAM is working perfectly by HAL_SDRAM _read.
How to handle SDRAM by DMA access specifically DMA _Read .
#define SDRAM_ADD_1 0xC0000000 #define SDRAM_ADD_2 0xC0000060
To me, if you are reading perfectly the data by writing and reading them back using the CPU it deas mean your FMC config is good.
Now I'm wondering if you are taking care of the cache coherency as you are transferring the data and reading them back using the CPU! refer to the AN4839 Level 1 cache on STM32F7 Series and STM32H7 Series/ 3.2 Example for cache maintenance and data coherency
2024-09-07 06:48 AM
Probably cache coherency, the debugger sees what the MCU returns and that might not reflect memory content if changed by hardware.
The pins and board wiring may not sustain the higher speeds.
The slower speed and RAS/CAS timing can be more accommodating. Yes you should be able to adjust other timings provided they still meet minimum requirements. Some of the integer divisions might force slower times as the granularity expands as frequency drops, but min timings are fixed and still need to be met.
Caching can hide much of this, especially as SDRAM have relatively high latency to get the first bytes out, subsequent ones being far less expensive. So well suited to cache line fills.
2024-09-10 01:04 AM
Hi,
Problem is with the DMA incorrect data is coming and Without the DMA is working properly .
I do agree with MCU pins (Nucleo Board) and SDRAM PCB pins connected via the jumper wire might be cause.
at this movement my question is Will the external SDRAM work with DMA mode in the F7 series DISCOVERY Boards ?.
One more question that how Touch GFX using an external SDRAM as buffer in Normal Mode or DMA mode ?.
2024-09-10 01:15 AM
Hi @MMARI.1 ,
@MMARI.1 wrote:
at this movement my question is Will the external SDRAM work with DMA mode in the F7 series DISCOVERY Boards ?.
I don't see how it's something related to the board. DMA works in the same way whatever the F7.
One more question that how Touch GFX using an external SDRAM as buffer in Normal Mode or DMA mode ?.
For TouchGFX, I kindly invite you to open a new thread in TouchGFX forum, TouchGFX team may help you.
2024-09-10 02:04 AM
hi,
I don't have the Discovery board but the SDRAM looks near to the MCU in the discovery board .
If the SDRAM works with the DMA mode in the Discovery Board then i need to make own pcb or i need buy the discovery board .
2024-09-10 03:00 AM
Hello,
@MMARI.1 wrote:
I don't have the Discovery board but the SDRAM looks near to the MCU in the discovery board .
If the SDRAM works with the DMA mode in the Discovery Board then i need to make own pcb or i need buy the discovery board .
Sorry didn't understand. The statement is not clear.
Also, what discovery board you are referring to? As you are talking about STM32F722 (in the original post), the only DISCO board compatible is the STM32F723E-Discovery that doesn't have SDRAM but PSRAM.
PS: I unselected the "Accept as Solution"