RTC is not working properly. (Vbat related problem)

[Seyoung]

We are making a board using stm32f767nih6. There seems to be a problem with RTC and Vbat while testing the board.

First, we are using LSE with a 32.768Khz external crystal oscillator. However, there is a symptom that it slows down by about 10 seconds during approximately 40 minutes.

Second, we have set up Vbat to supply 3.3V using a coin battery. However, when the power is turned off and turned on after a certain period of time, the RTC restarts around the point where the power was turned off.

For example, when the power is turned off at 10:00 and turned on at 10:30, the time displayed on the device is 10:00.

[Andrew Neil]

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@Seyoung wrote:

we are using LSE with a 32.768Khz external crystal oscillator.

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That's just a crystal - not a crystal oscillator:

https://community.st.com/t5/stm32-mcus-products/stm32f4-osc-problem/m-p/664136/highlight/true#M241592

[PGump.1]

Hi,

I think that you don't have the LSE enabled.

Kind regards
Pedro

[Peter BENSCH]

@Seyoung The behaviour sounds very unusual. At first I assumed that you were inadvertently using the free-running LSI instead of the LSE as the clock source for the RTC. However, 10s deviation within 40min, which corresponds to 4167ppm, is far too much even for LSI. Perhaps you should add the programming of the RTC and LSE here.

Regards
/Peter

[Seyoung]

 

   

[PGump.1]

Hi,

I'm going to suggest the crystal capacitance loading is far too high, making it run slow, and when it switches to VBAT it stalls...

Kind regards
Pedro

[Peter BENSCH · Accepted solution]

I have just checked the parameters of your crystal again: the CFS-20632768DZFB specifies Rs=35kohms, C0=1.2pF and CL=12.5pF (variant F).

The STM32F767 has four drive modes for the LSE: low, medium low, medium high and high. The default value is 0 (see RM0410, section 5.3.20), which results in LSEDRV[1:0]=00 = Low Drive.

I then calculated the values of the crystal according to AN2867 and obtained the following for the gain margin, which must always be above 5:

• Low: 2.155
• Medium Low: 3.367
• Medium High: 7.631
• High: 12.12

If you set the LSE drive level from Low to at least Medium High in your initialisation routine, LSE should at least work properly (assuming a suitable layout). It is important to enable write access to the backup domain beforehand. Until this is possible again in CubeMX, you can insert this after SystemClock_Config(); in the block /* USER CODE BEGIN SysInit */:

HAL_PWR_EnableBkUpAccess();
__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_MEDIUMHIGH);
HAL_PWR_DisableBkUpAccess();

Once again: the observed deviation of 10 seconds within 40 minutes will probably be reduced at best, but it may also have other reasons, e.g. the layout.

Regards
/Peter