We are creating a driver for a W25Q128JV Winbond Nor Flash chip. We are working with a STM32 H743ZI2 board and communicating on the QSPI peripheral with the help of the HAL libraries. Currently the driver can successfully Write to the chip using standard Page Program (0x02h) and the Quad Page Program (0x32h). We are also successfully doing a Fast Read (0x0Bh) up to speeds of 72MHz and a Fast Read Dual Output (0x3Bh) up to speeds of 36MHz before they start to fail. Currently we are using a 3.3V power bus, so based on the AC Electrical Characteristics seen in the datasheet we expect these commands to work up to speeds of 133MHz.
If you prefer the generated code that is also provided below.
QSPI_HandleTypeDef hqspi;
/* QUADSPI init function */
void MX_QUADSPI_Init(void)
{
/* USER CODE BEGIN QUADSPI_Init 0 */
/* USER CODE END QUADSPI_Init 0 */
/* USER CODE BEGIN QUADSPI_Init 1 */
/* USER CODE END QUADSPI_Init 1 */
hqspi.Instance = QUADSPI;
hqspi.Init.ClockPrescaler = 12 - 1;
hqspi.Init.FifoThreshold = 4;
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE;
hqspi.Init.FlashSize = 23;
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_6_CYCLE;
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
hqspi.Init.FlashID = QSPI_FLASH_ID_1;
hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
if (HAL_QSPI_Init(&hqspi) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN QUADSPI_Init 2 */
/* USER CODE END QUADSPI_Init 2 */
}
void HAL_QSPI_MspInit(QSPI_HandleTypeDef* qspiHandle)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
if(qspiHandle->Instance==QUADSPI)
{
/* USER CODE BEGIN QUADSPI_MspInit 0 */
/* USER CODE END QUADSPI_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_QSPI;
PeriphClkInitStruct.PLL2.PLL2M = 32;
PeriphClkInitStruct.PLL2.PLL2N = 144;
PeriphClkInitStruct.PLL2.PLL2P = 2;
PeriphClkInitStruct.PLL2.PLL2Q = 2;
PeriphClkInitStruct.PLL2.PLL2R = 2;
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_1;
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* QUADSPI clock enable */
__HAL_RCC_QSPI_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**QUADSPI GPIO Configuration
PF6 ------> QUADSPI_BK1_IO3
PF7 ------> QUADSPI_BK1_IO2
PF8 ------> QUADSPI_BK1_IO0
PF9 ------> QUADSPI_BK1_IO1
PF10 ------> QUADSPI_CLK
PB10 ------> QUADSPI_BK1_NCS
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF10_QUADSPI;
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_10;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF9_QUADSPI;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* QUADSPI interrupt Init */
HAL_NVIC_SetPriority(QUADSPI_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
/* USER CODE BEGIN QUADSPI_MspInit 1 */
/* USER CODE END QUADSPI_MspInit 1 */
}
}Here are the functions we are working with to drive the flash chip and the instruction description from the datasheet.
uint8_t QSPI_SetBurstWrap_77h(uint8_t mode) {
if (mode < 0 || mode > 7) {
mode = 1;
}
mode = mode<<4;
QSPI_CommandTypeDef sCommand;
/* Burst Wrap Sequence --------------------------------- */
sCommand.Instruction = SET_BURST_WRAP_CMD;
sCommand.InstructionMode = QSPI_INSTRUCTION_1_LINE;
sCommand.AddressMode = QSPI_ADDRESS_NONE;
sCommand.AddressSize = QSPI_ADDRESS_24_BITS;
sCommand.Address = 0;
sCommand.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
sCommand.DdrMode = QSPI_DDR_MODE_DISABLE;
sCommand.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
sCommand.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
sCommand.DataMode = QSPI_DATA_4_LINES;
sCommand.NbData = 1;
sCommand.DummyCycles = 6; //24 Dummy Cycles across 4 Lines 24/4=6
if (HAL_QSPI_Command(&hqspi, &sCommand, HAL_QPSI_TIMEOUT_DEFAULT_VALUE)!= HAL_OK) {
return HAL_ERROR;
}
/* Transmission of Wrap Bits */
if (HAL_QSPI_Transmit(&hqspi, &mode, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
{
return HAL_ERROR;
}
return HAL_OK;
}Finally, the main we are using for our tests is below.
/* USER CODE BEGIN 0 */
uint32_t Size = 4096; //4KBytes
uint32_t ReadAddress, WriteAddr, BlockAddress = 0;
uint8_t sData[4096];
uint8_t rData[4096];
uint8_t s1Data[4096];
uint8_t checkReg;
/* USER CODE END 0 */
int main(void)
{
/* Enable I-Cache---------------------------------------------------------*/
SCB_EnableICache();
/* Enable D-Cache---------------------------------------------------------*/
SCB_EnableDCache();
/* MCU Configuration--------------------------------------------------------*/¬
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* USER CODE BEGIN Init */
int i=0;
uint8_t val= 0x00;
while(i < Size){
sData[i] = val;
if ((i+1) % 1 == 0) {
val+=1;
}
i++;
}
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_QUADSPI_Init();
/* USER CODE BEGIN 2 */
/*Enable Quad*/
QSPI_EnableQuad(); //Set the QE, DRV0, DRV1 bits
/*Erase Functions*/
if (QSPI_EraseSector_20h(BlockAddress) != HAL_OK) {
Error_Handler();
}
/*Read Single Data Lines*/
if (QSPI_FastReadData_0Bh(rData, ReadAddress, Size) != HAL_OK) {
Error_Handler();
}
/*Read Quad Data Lines*/
if (QSPI_FastReadQuadOutput_6Bh(s1Data, ReadAddress, Size) != HAL_OK) {
Error_Handler();
}
while (1)
{
}
/* USER CODE END 3 */
}Before we do any read or write operations we write to and check the values in our status registers to ensure the QE bit is set to 1 and that DRV1 and DRV0 are set to 0 making the Driver strength 100%.
Here are the register values we read out after doing our setup for Default Driver Strength 25%:
Logic Analyzer of Fast Read Quad Output
I attached the .h file that contains the masking of the hex instructions just in case
We have also conducted some testing that might be of interest.
One thought we had was that the handling of the WP and HLD lines were not being switched to high impedance correctly. To test this, we disconnected the IO3 from the Nucleo board and probed both the IO3 on the Winbond chip and the Nucleo board with the logic analyzer to see all the data transmission that is happening. For the first test we had the IO3 line connected during initialization and then disconnected it and probed the data on both sides the results of this are below
Here is what I am seeing in the hqspi registers. I have set Sample Shifting to the default (None) but have tried using the shift by half cycle and have not noticed any difference in performance.
To clarify I preform 1 write and then try to read it in single data mode using fast read which correctly reads back all the data confirming that the data on the chip was written. I then try the Quad-I/O or the Quad Fast Read, both of which only get 16 bytes of expected values it seems to hang and then get a bunch of noisy data that looking at the logic analyzer seems like it might be coming from the nucleo boards side. I've attached larger LA captures in case it helps point to some obvious clues.
IO3 Connected During Initialization
Thanks for the notes on things to change and for pointing me towards the errata sheet. There are two examples in there that could be causing things to hang. I will try out these changes this week and come back with the results of those changes.
