[POSSIBLE SILICON BUG] STM32G474QE Analog Sequencer on ADC4 Slips by one when configured for dual regular mode with DMA under specific trigger settings and high noise on inputs.

[KYin.2]

I am currently using an STM32G474QE for a motor control application and ran into a possible silicon bug.

We have ADC1 and ADC2 configured for dual regular interleaved mode with DMA triggered off TIM1_TRGO2

ADC3 and ADC4 configured for dual regular interleaved mode with DMA triggered off TIM1_TRGO

TIM1_TRGO is set to TIM_TRGO_UPDATE

TIM1_TRGO2 is set to TIM_TRGO_OCRef4RisingOCRef6Falling

Here is the issue. Under high load (and noise on the adc inputs), the analog sequencer on ADC4 slips by one, and as a result, all the samples transferred by DMA are in the wrong indices, i.e. ADC3 is converting regular conversion rank 1 while ADC4 is converting regular conversion rank 2 when instead they need to be converting the same regular conversion rank. ADC3 and ADC4 are supplying the current and temperature measurements to the motor control loop. The result is usually catastrophic failure. At best, the motor makes a rattling sound due to current waveform distortion, at worst the motor locks up entirely and the energy returned into the inverter destroys the MCU.

Changing TIM1_TRGO to TIM_TRGO_OCRef4 fixes the issue, i.e. unable to reproduce observed behavior when TIM1_TRGO setting is changed to the above.

I am wondering if there is any way to verify this or if ST could explore further and possibly add it to the errata?

Thank you

[Singh.Harjit]

Which revision of the part is this?

[KYin.2]

I'll have to double check, but I think it was rev Y.