NSS the output ignores the settings, and according to the waveform, the outputs are in the hiz state, because you can see the leads that are not damped by pressing to the ground. (STM32F303)

[placidity.master_gmail.com]

NSS the output ignores the settings, and according to the waveform, the outputs are in the hiz state, because you can see the leads that are not damped by pressing to the ground.

 (STM32F303)

   //   Bit 4 FRF: Frame format

   //   0: SPI Motorola mode

   //   1 SPI TI mode

   //   SPI2->CR2 |= 1<<4;

   //   Bit 3 NSSP : NSS pulse management

   //   This bit is used in master mode only. it allow the SPI to generate an NSS pulse between two

   //   consecutive data when doing continuous transfers. In the case of a single data transfer, it

   //   forces the NSS pin high level after the transfer.

   //   It has no meaning if CPHA = ’1’, or FRF = ’1’.

   //   0: No NSS pulse

   //   1: NSS pulse generated

   //   Note: 1. This bit must be written only when the SPI is disabled (SPE=0).

   //   2. This bit is not used in I2S mode and SPI TI mode.

   SPI2->CR2 |= 1<<3;

   //   Bit 2 SSOE: SS output enable

   //   0: SS output is disabled in master mode and the SPI interface can work in multimaster

   //   configuration

   //   1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI

   //   interface cannot work in a multimaster environment.

   //   Note: This bit is not used in I 2 S mode and SPI TI mode.

   SPI2->CR2 |= 1<<2;

[waclawek.jan]

According to RM, you are not supposed to set NSSP and CPHA simultaneously.

Try with CPHA=0.

JW

[placidity.master_gmail.com]

thanks for the tip

yes, with CPHA=0, NSS works as it should, but there is another problem, in the documentation

for LTC6804, in the description of the 4-wire SPI interface, it is specified:

"the 4-wire serial port is configured to operate in a SPI

system using CPHA = 1 and CPOL = 1. Consequently, data

on SDI must be stable during the rising edge of SCK."

and in the description of isoSPI it is not specified about a phase and other,

but I so understand that isoSPI has to send signals according to logic of 4 wire SPI

"Standard SPI signals are encoded into differential pulses."

it turns out that STM will not be able to communicate with LTC6804 ?

[placidity.master_gmail.com]

yes, with CPHA=0, NSS works as it should, but there is another problem, in the documentation

for LTC6804, in the description of the 4-wire SPI interface, it is specified:

"the 4-wire serial port is configured to operate in a SPI

system using CPHA = 1 and CPOL = 1. Consequently, data

on SDI must be stable during the rising edge of SCK."

and in the description of isoSPI it is not specified about a phase and other,

but I so understand that isoSPI has to send signals according to logic of 4 wire SPI

"Standard SPI signals are encoded into differential pulses."

it turns out that STM will not be able to communicate with LTC6804 ?

[placidity.master_gmail.com]

I didn't see the "show more answers" button, and now I can't delete the repeated post. I thought that it was not preserved.

[waclawek.jan · Accepted solution]

I had a look at the LTC6804 and it appears to be a very complicated chip and I am not going to try to understand its working. However, this

CSB must remain low

for the entire duration of a command sequence, including

between a command byte and subsequent data.

indicates, that the STM32 SPI NSS pulsing mode is not usable for your case anyway.

So, the best thing to do is to set NSS to GPIO, and control it "manually", according to the required protocol.

JW

[placidity.master_gmail.com]

thank you for advice.

I suspected it, but I wasn't entirely sure.

due to little experience.

processing CSB manually is in theory a problem,

because the CPU can be distracted by interrupts,

and the time diagrams will float away,

and it is difficult to imagine what will happen in the end.