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according to the documentation for the iic bus, devices must create start conditions, even if the devices ignore the ACK bit, but stm32f103, in fact, ignores the start bit without the ACK bit. if this is not the case, then where is it written in the ...
in RM0008 Rev 21; page 1083; Table 220. Flexible SWJ-DP pin assignment"The default state after reset is “000�? (whole pins assigned for a full JTAG-DPconnection). Only one of the 3 bits can be set (it is forbidden to set more than one bit)."I don't u...
in RM0008 Rev 21page 775Bits 5:0 FREQ[5:0]: Peripheral clock frequencythe description of the frequency divider is extremely unclear. there is no formula for where the input is, how it is divided, where the output is. what if I want to set strictly 50...
PM0056, Rev 6, page 105, Table 33. STM32 core peripheral register regions,Nested vectored interrupt controller; twice ?0xE000E100-0xE000E4EF Nested vectored interrupt controller0xE000EF00-0xE000EF03 Nested vectored interrupt controller
PM0056, Rev 6, page 91, Table 30. Branch and control instructionsCBNZ     Compare and Branch if Non ZeroCBZ     Compare and Branch if Non Zeroreally ?but later :3.8.6  CBZ and CBNZCompare and branch on zero, compare and branch on non-zero.
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