No 2020 STM32 wishlist
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‎2020-06-19 03:29 PM - edited ‎2023-06-18 09:38 PM
This is probably the promised replacement.
[Edit 2023] Link above lead to Ideas, a section mostly ignored by ST (TouchFX crew being exception) and ultimately removed together with content i.e. user wishes when migrating to Khoros [/EDIT]
Pity. It's been a nice tradition.
JW
PS. Following is my 2020 STM32 wishlist. I'm not going to dump it to that new place. Anybody feel free to cherry-pick and post there, if you feel so.
- renew STM32 Technical Updates https://community.st.com/s/question/0D50X00009Xkba4SAB/stm32-technical-updates
- normal forum software
- make a static snapshot of the forum, especially since older posts are closed
- revert ST main web to pre-2019 (practically every "improvement" made in 2019 is a regression in usability) - this would also return full linkability
- more technical staff presence in the forum
- in documentation, better module-interconnections description (these chapters are often incomplete or missing), links from RM to AN where the interconnections are described "externally"
- in new chips, more interconnections, especially timer-related, e.g. SPI (and other modules') baudrate generated by timer, SPI NSS/framing generated by timer in counter mode (i.e. timer fed from SPI), USART IDLE timer, etc.
- as an upgrade to TIM module, add a shift register to facilitate non-standard shiftregister-based communication protocols
- add a simple counter to RTC (while done in RTCv3, present only in 'WL, see AN4759)
- document variants of IPs used in the various STM32 models
- extensive examples based on normal C code (Snippets)
- dozens of appnotes (https://community.st.com/s/feed/0D50X00009XkVvLSAV)
- update ES timely (errata often don't make it from the particular model where they've been "discovered" into other models where the same erratum applies, or it takes inordinate amount of time when this happens, and often such "migrated" erratum misses some key part e.g. https://community.st.com/s/question/0D50X0000BufujjSQA/es0388-l452-errata-rev5-comment-about-mco-in-spurious-brownout-reset-after-short-run-sequence-erratum-does-not-make-sense-without-the-accompanying-figure )
- remove "modern feel and look" in technical texts (appnotes, errata, devboards UM)
- reduce unnecessarily big images in devboards UM, reducing file size to sane values
- include schematics in the devboard UMs, even if its more work for you, it's then less work for us
- reconsider DISCO boards - make them to be perks, break out all pins and make ways to disable onboard features, make examples, make the stlink to be usable (e.g. make appnote how to use it with low-voltage target, how to use galvanic decoupling, how to use swo?)
- remove obsolete devboards (e.g. STM32VLDISCOVERY with the V1 STLink which is not supported anymore) - and by that I mean purge them also from the distributors -- OTOH, make available documentation also for discontinued devboards
- provide binaries of ALL the demos which come preprogrammed in ALL the DISCO, NUCLEO and EVAL board
- provide sources for MFX on Disco boards
- stlinkv2-1 in the lower-end devboards rather than the unnecessarily expensive stlinkv3 (which btw. can't provide the 8MHz clock precisely)
- stlinkv2-1 sold as a chip (preprogrammed 'F103)
- STLinkV3 implement complete FS functionality, so that it can be used with USB isolators https://community.st.com/s/question/0D53W000005qNEzSAM/how-can-isolate-the-usb-port-for-stm32g474-nucleo-64-board https://community.st.com/s/question/0D53W000003Kqb3SAC/failed-to-connect-to-stlink-v3-using-a-usb-isolator
- crypto-less 'F7x0/'H7x0 https://community.st.com/s/question/0D50X0000ALv1isSQB/not-really-a-technical-questionproblem-purchasing-stm32h750vb
- direct sales distributor in Europe (yes I'm selfish)
- built-in JVM in the java-based software (including the installers) https://community.st.com/s/question/0D70X00000763nW/oracle-jre-license-impact
- bitfield values in the CMSIS-mandated device headers https://community.st.com/s/feed/0D50X00009XkVsDSAV
- restore pin compatibility across families (G0/G4 are not compatible, not even with each other)
- consider API to USB library portions in bootROM (see NXP's LPC)
Others have asked for:
- more 32-bit timers
- chips with smaller and/or more prototyping-friendly packages
- better GPIO/AF matrix
- use the wide ADC MUX also as input MUX to OPAMP/PGA
- more transparent software update process (public bug tracker), maybe even open (parts of ) it to external contributions
- more chips with integrated HS USB PHY
- shared address/data bus (i.e. stripped-down pin requirement, possibly fitting into 100-pin devices) for SDRAM, as Tiva do https://community.st.com/s/question/0D53W000003xcVSSAY/how-to-configure-sdram-on-100-pin-h7
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‎2020-06-20 08:36 AM
I don't understand why "AF" has to be separate, AF register could also specify input/output. My suggestion:
AF0: INPUT (GPIO)
AF1: OUTPUT, opendrain, pulldown only (use with pullup).
AF2: OUTPUT, opendrain, pullup only (use with external/internal pulldown).
AF3: OUTPUT, pushpull.
Now make UART_RX an AF in one of the 0bxx00 Alternates. And UART_RX is 0bxx11. Note that the "enable" to the top and bottom output mosfet are (often) simply driven by the lower bits of the AF register. It does break the "AF11 is ETH" rule that is now in place. Anyway, that's how I'd design the AF/GPIO system. Current stuff is quite "spread out" over multiple registers, that could be simplified both for software and for the hardware.
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‎2020-06-21 07:33 AM
ST-LINK V3 fixed so it outputs a xtal generated clock on Nucleo PCBs
USB HOST Hub support
Combine H7A3/H743 to get 480MHz part with 1Mb of contiguous memory
More and better example software for Nucleo PCBs. e.g SDMMC using a readily available SDcard socket, QuadSPI flash etc.
DACs and LTDC not sharing pins on 144-pin parts
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‎2020-06-21 11:53 PM
A few wishes -
- more timers that can be clocked by the LSE. Ideally most timers should have this as an option.
- code snippets (as mentioned above), or something similar to help those trying to get a peripheral up and running quickly via registers.
- some simple way for me to be able to take advantage of the lower power consumption offered by the SMPS, without having to use inductors and flea-sized surface mount packages (for the external regulator). eg. a SOT-23 and some capacitor-only (charge-pump) scheme would suit me better
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‎2020-06-22 12:12 AM
some simple way for me to be able to take advantage of the lower power consumption offered by the SMPS, without having to use inductors and flea-sized surface mount packages (for the external regulator). eg. a SOT-23 and some capacitor-only (charge-pump) scheme would suit me better

That is not possible. Consider a 1uF capacitor charged to 5V. A second 1uF capacitor is currently discharged. We activate a switch between them and the charge shares between the two caps, 2.5V, both of them. Now consider the energy. E = 0.5 C U^2 = 0.5 * 10^-6 * 25 = 12.5uJ. Good. Now after sharing E = 2 (twocaps) * 0.5 * 10^-6 * 2.5^2 = 6.25uJ : half of what we started with.
So when we use a switching element with a resistance of say 1 Ohm, the equalisation will take roughly 5 microseconds to complete for 99%. Now you can calculate that the ressitor took that 6.25 uJ of energy. If you use an ideal switch (0 Ohms) the losses will end up in the ESR of the capacitors. There is nothing you can do to prevent energy loss.
But yes: Integrated switch mode DCDC would be nice. So now we have an internal 1.2V regulator that generates the power for the core. Integrate the SMPS controller and: there is a quite low current requirement that is known in advance, so quite possible to do this with just one pin and one external component (the inductor).
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‎2020-06-22 02:41 AM
Oh dear.... reality gets in the way of my dreams. I thought if it was easy to give me the power savings of the SMPS in an easy form it would have been done already. But I am glad that greater minds are working on the problem than me. I added it as a sort of wish in the category of wishing for world peace.... thanks.
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‎2020-06-22 02:52 AM
Your proposal does not make sense. Pull Up/Down and Open Drain are properities on top of the peripheral proerities of a GPIO
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‎2020-06-22 03:05 AM
Uwe, First, let me recognize that my GPIO-reform is one that would be incompatible in software, thus now with hundreds of different CPUs already "in the field" this is not realistic to change now.
I agree that the pullup and puldown are simply a bit that cannot be optimized to less than one bit each. (well.... from the four possible options, only three are used, pullup AND pulldown enabled at the same time doesn't really make sense. Although... By enabling them both and finding a 0.5-2.8V analog voltage on the pin you can detect "nothing digital connected")
But I was talking about the actual push-pull output fets. Disable them both, and the pin is an input. Enable only the bottom N-fet and the pin is opendrain. Enable them both and the pin is pushpull output. Again the fourth combination is funny. In this case, I'm not sure if it is documented and/or currently possible, but enabling only the top P-FET will also result in an opendrain output, but now with the other polarity. With the normal opendrain outputs you can make a wired-and (any participant can pull it low, all of them have to drive high to make the signal high). With the other polarity you get the wired or. Anybody can make the signal low.
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‎2020-06-23 03:04 AM
Hello
my wish list
- More flexible interconections matrix
- Multi channel SPI mode for chips like ADS8355 (Dual or quad MISO or MOSI )
- Multi channel CS pin (multi dievices on the same SPI)
- Timer for delayed CS signal (Dalay for some ADC or DAC's)
- More precision, and faster ADC, DAC with PGA,
- HW debouncing for mechanical button switches
- Faster SPI and I2C (for example 3,4 MHz I2C)
- Double buffer mode for DMA (CubeMX config )
- Timer triggered dma form most perifery (CubeMX confiq)
- Tool in CubeMX for DSP Filter design
- Tool in CubeMX for FMAC (G4)
12.Calculators for Timer or ADC bulid in CubeMX ( I want to see usnits such as ms or MSPS directly in CubeMX)
13.New function HAL_Delay_us(), HAL_Delay_ns
14.DARK MODE for all Cube software (vivid white-blue colors are burns my eyes)
15.Better forum (ideal forum looks like this https://www.eevblog.com/forum/projects/)
16.More examples for every periphery and mode
17.Better IDE (simpler and faster IDE without a million unnecessary functions, see Segger, IAR, Keil)
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‎2020-06-23 05:05 AM
H7 wish list:
DTCM-SRAM working with DMA.
Another RMII pinout option from PE7 to PE15 or from PD8 to PD15
Lower cost variants with less flash and AXI-SRAM.
Upgrade the timers and analog peripheras to ones of the STM32G4.
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