How to configure SDRAM on 100 pin H7

[DReis.1]

I am trying to set up the config for a new ST project, but I cannot make the FMC configuration select SDRAM. The tool lets me select the SDRAM mode for different package versions, like the BGA configuration, but not for the 100pin alternative. This has been mentioned in forum posts like this, and I follow the advice to see, in table 9 of DS12110 Rev7 that I should be able to use the SDRAM pins on the 100pin package. I need to exercise the ADC/DMA to write to SDRAM because the application requires a long collection that would be much too big to store internally. Please help me understand how to configure this part to use SDRAM. Or definitively confirm that SDDRAM controller is not possible with the 100pin package.

Thanks, Darren

[waclawek.jan]

> I follow the advice to see, in table 9 of DS12110 Rev7 that I should be able to use the SDRAM pins on the 100pin package.

Okay so show us, in that table, the mapping, to which STM32H7 pins do you connect the SDRAM pins?

JW

[DReis.1]

Well, I think they connect to 37-45, 55-57, 61,62 for the FMC_Di 16 pins, 63-65 for NE type pin, 84-86 for clock and so on. I can't tell if this means SDRAM works for the LQFP part.

[waclawek.jan]

And address lines?

The 100-pin package lacks the lower addresses (A0-A12 and also BA0-BA1), and that's showstopper for SDRAMs.

The 'H7 documentation is still very immature - this fact, together with a FMC pin assignment table, is a staple content of the 'F4/'F7 datasheets.

JW

[DReis.1]

That's informative, thank you. I'm coming from a TIVA project where we shared the Address and Data pins on the MCU so that the total pin connections was 32 (for 16bit data). The exchanges first programmed the address on the data lines and then the data itself, as shown here. What I think you're saying is that there is no way to mux the address and data pins, they are all needed in parallel. That would certainly require way more pins.

Darren

[DReis.1]

as a side question, can i assign the SD related operations by hand to GPIO? Is there a higher level config controller that I could write to make the normal FMC work?

[TDK]

STM32CubeMX will happily do this for you.

Edit: I was using LQFP144, not LQFP100. There is no SDRAM configuration available on LQFP100.

> as a side question, can i assign the SD related operations by hand to GPIO?

Not sure what you mean. You have to use the SDMMC peripheral for SD functions. No way you're going to bit bang those with any amount of speed.

[waclawek.jan]

As for the shared address/data scheme as you've outlined above (from the Tiva manual) - interesting concept, but I don't think the STM32 FMC module supports this, see SDRAM controller subchapter of FMC chapter of RM.

As TDK said (pointing out that SD is Secure Digital (for which SDMMC is the interace to be used) - but the same is valid for SDR SDRAM (Single Data Rate Synchronous Dynamic RAM)), you can bitbang the interface, but you are not going to achieve any reasonable speed.

JW

[DReis.1]

Thanks, bitbanging is what I was thinking about. I guess you're right, that won't be very fast. Thanks for your help team.

D