@alister , Below are the details of my implementation,
I am doing this for just RAM testing at present,
* I am using the BSP driver for APS6408L provided by ST for the B-U858I-IOT02A Discovery Kit thats uses OSPI DTR in memory mapped mode.
* I have been trying to test the RAM by disabling the cache(although I did try enabling it and did not see any difference)
* For testing I have PSRAM read and write functions, that read and write in 32 bit aligned word on the PSRAM. I am only copying test data from SRAM to PSRAM(without using the DMA). My read and write functions are below,
uint32_t ReadMemory(uint32_t address, uint8_t* data, uint32_t size)
{
// address and size should be 32bit aligned
if (address % 4 != 0 || size % 4 != 0)
{
return 1;
}
if ((address + size) > (max_ram_addr + 1))
{
error_status = 2;
}
else if (error_status == MemErrorStatus::eNoError)
{
volatile uint8_t* ram_ptr = reinterpret_cast<volatile uint8_t*>(OCTOSPI1_BASE + address);
etl::copy(ram_ptr, ram_ptr + size, data);
}
return 0;
}
uint32_tExtRam::WriteMemory(uint32_t address, const uint8_t* data, uint32_t size)
{
// address and size should be 32bit aligned
if (address % 4 != 0 || size % 4 != 0)
{
return 1;
}
// Check memory size out of bound
if ((address + size) > (max_ram_addr + 1))
{
return 1;
}
else if (error_status == MemErrorStatus::eNoError)
{
volatile uint8_t* ram_ptr = reinterpret_cast<volatile uint8_t*>(OCTOSPI1_BASE + address);
etl::copy(data, data + size, ram_ptr );
}
return 0;
}
The read and write testing appears to be working when the size of data >= 1024. I do have a confusion here though, does the write needs to be page boundary aligned. e.g. Is it possible to write 1024bytes at address OCTOSPI1_BASE + 4?
* If I do not use Dcache, my assumption is that the cache flushing does not matter.
--Rikesh
