STM32u585 Memory Mapped Read/write on B-U585I-IOT02A

[rikeshshakya]

While using memory mapped mode for APS6408L using STM32u585 on B-U585I-IOT02A, how is the row boundary crossing handled?

* If I want to write across multiple Rows in memory mapped mode, do I need to handle this manually or is it automatically handled by the memory controller?

* Is it possible to write at any even address with data of any length or is there any limitation on the maximum size of data that can be written in single instructions like using memcpy?

[Tesla DeLorean]

Not sure how many posts you're going to make on this topic? At some point it becomes duplicative

You had an audience over here  https://community.st.com/t5/stm32-mcus-products/memory-mapped-mode-write-sizes-for-psram-aps6408l-on-b-u858i/m-p/663232#M241314

I'd assume if you can't tell the memory controller the page size / boundaries, it's not going to do it automagically..

Probably some wrapped aligned memcpy() or 32-bit wide load/store 

[rikeshshakya]

Sorry for the confusion @Tesla DeLorean , My other post was related to the write size and this one is related purely to the use of memory mapped mode. Hence, I thought it might be better to have separate post.

My assumption was that the memory controller will be handling the page size/boundary automatically. However, since I could not get my test working, I was just wondering if it is the hardware limitation or something that has to be handled in the software.

[Tesla DeLorean · Accepted solution]

I don't have a problem either way, I just think that you'd assembled most of the interested parties in the other thread, so pressing the issue there would get the most traction.

To say the Serial RAM implementation is clumsy is probably generous. I'd expect you'd need to do some burst LDM/STM type action on the MCU, taking care not to cross the page boundaries. I'd probably do some generalized wrapped memcpy type functionality which had an awareness of the memory regions, and then behaved accordingly to ensure the interaction was compatible with the memory.

Buffered writes, and cache flushing likely to complicate things on Cortex-M7's

Would look to see if the Memory Mapped Write template provides for a page size, or burst length. Without such things the STM32 side controller is unlikely to be sufficiently aware of the needs of the memory IC

[rikeshshakya]

Thanks @Tesla DeLorean for your feedback, I am closing this ticket as I agree this might have created confusion from being a kind of duplicate discussion. I have added my comments in the previous ticket.