Showing results for 
Search instead for 
Did you mean: 

LDREX instruction on the STM32H755 when MPU activated causes hard fault

Associate III

Hello guys,

I had recently a problem with executing LDREX instruction on the STM32H755 when MPU was activated for the specific memory region that covered the address accessed by the LDREX instruction. After executing LDREX instruction I got immediately a hard fault error with BFARVALID & PRECISERR bits are set in BFSR and the last accessed address pointed on the address accessed by the LDREX instruction. When the MPU was not activated there was no problem at all.

Before I provide the MPU configuration I would like to ask few questions:

1. Has the STM32H755 implemented a global monitor of the exclusive accesses?

2. Is the exclusive access cleared in the global monitor after ISR occurs on the CPU that claimed it, or only the local one is cleared?

The MPU configuration is following:

  MPU_InitStruct.Enable = MPU_REGION_ENABLE;

  MPU_InitStruct.Number = MPU_REGION_NUMBER0;

  MPU_InitStruct.BaseAddress = someAddress;

  MPU_InitStruct.Size = 2;

  MPU_InitStruct.SubRegionDisable = 0x00;

  MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;

  MPU_InitStruct.AccessPermission = MPU_REGION_PRIV_RW_URO;


  MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;

  MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;

  MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;


Hi, this is the correct answer, I found it out already but I was too lazy to post it. :D

>>If ST is monitoring this post, would you please confirm that the STM32H7 does not implement a global exclusive monitor?

I'll flag for review, but if ARM didn't directly facilitate this, ST surely didn't implement it, these types of thing get massively complex, really quickly, and mechanics to make them work introduce all kinds of potential to defer, or stall, or otherwise dead-lock things.

Tips, buy me a coffee, or three.. PayPal Venmo Up vote any posts that you find helpful, it shows what's working..
Associate III

Actually I got this info from ST directly, I created a support ticked, here is the answer from ST:

We don't implement global monitor on STM32H7. We recommend to use the HW semaphore for synchronization.

Best regards

I thought it completely explains my findings, however it does explain all but why normal memory with shareable attribute also does not work?

Presumably that's because the STM32H7 does not implement a global exclusive monitor in the AXI interconnect, and so it doesn't support exclusive access.