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milorad · 2024-10-01

I am using STM32U585 and I stumbled upon the following problem:If a device is configured with TrustZone enabled (TZEN=1) there is different behavior in the following situations:1. SPI is configured without DMA and CPU is running non-secure code in pr...

milorad · 2017-09-28

Posted on September 28, 2017 at 14:11I'm working on an USB Device driver and I want to receive multiple isochronous packets per micro-frame (on high-speed of course).As it is nowehere mentioned in errata, I asume it should be working, however there ...

milorad · 2024-10-03

Just to close this question by myself for anyone stumbling upon same problem in future.In the “AN5347 - Arm® TrustZone® features for STM32L5 and STM32U5 Series“ it says “All memory map is fully secure through the IDAU/SAU, until the secure code enabl...

milorad · 2024-10-01

Hi liaifat85,thanks for quick answer.I actually would like to understand how is that CPU running non-secure code can access secure SRAM1?I suspect that DMA uses different bus and it checks secure attribute, and that for CPU access to RAM secure attri...

milorad · 2022-01-21

I thought it completely explains my findings, however it does explain all but why normal memory with shareable attribute also does not work?

milorad · 2022-01-20

Thanks for that, it does completely explain my findings.

milorad · 2022-01-16

That cannot be the reason since I have set up memory accessed by LDREX as Device memory in this case and according to ST's application note AN4838 to prevent speculative prefetch, memory should be set up as Strongly-Ordered or Device and I tried both...

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STM32U5 TrustZone enabled DMA problem

USB Device high-bandwidth isochronous transfers

Re: STM32U5 TrustZone enabled DMA problem

Re: STM32U5 TrustZone enabled DMA problem

Re: LDREX instruction on the STM32H755 when MPU activated causes hard fault

Re: LDREX instruction on the STM32H755 when MPU activated causes hard fault

Re: LDREX instruction on the STM32H755 when MPU activated causes hard fault