Jitter in ADC+DMA mode

[Gaston]

Hi,

I've configured 3 ADC channels (IN2, IN3,IN4) in DMA mode (device=STM32L475RCTX running at 80MHz) as shown:

  

I want to set a sample time of 6400Hz (156.25ms) so here's the TIM4 configuration

 

In order to test the sample time I toggle an output pin in the irq callback:

  

Everything is okay except for the jitter on this output:

 

This jitter is about of 5us. Why? How can avoid this? I've tried to change the DMA priority interrupt without success.

thanks in advance,

gaston

[waclawek.jan]

This site uses salesforce instead of normal forum software. Salesforce does not embed pictures upon copy/paste, even if they appear to be embedded. You have to upload them manually, click on the "picture" icon in the line at the bottom of edit window.

Or, better, add code as, well code (i.e. text).

If you toggle a pin in ISR (DMA Transfer Complete), then the jitter may come from both the DMA's transfer being influenced by collisions on the bus, and - probably more importantly - jitter of the interrupt's latency. This does not mean, the ADC is jittery.

You may be able to observe ADC's sampling directly, if you connect to its input a relatively high impedance signal source (e.g. simply a 10kOhm resistor to ground or VDDA) and observe using oscilloscope.

JW

[Kraal]

Hi,

The ADC is configured in asynchronous mode. In the reference manual RM0351 on the page 510, the note tells you that if you want to have no jitter, then you need the synchronous option. The reference manual for the F0 family is clearer on this point.

So what you see is the jitter on the start of the conversion, maybe with a mix of the ISR of ADCConvCplt execution jitter as @Community member​ suggested.

Again if you want to make sure that the start of conversion has no jitter, follow @Community member​ suggestion on using a scope on the analog source.

Best regards,

Kraal

[Gaston]

About inserting images/code, understood. I've done as you've suggested. Thanks.

On the other topic you claim that ADC has no jitter but I don't understand how can I observe the sampling frequency by connecting the ADC input to a High-Z signal source. Could you explain it in more detail?

gaston

[waclawek.jan · Accepted solution]

At the start of sampling period, the internal sampling capacitor is switched on, potentially causing a dip in the input signal observable by oscilloscope, if the signal impedance is relatively high.

JW

[Gaston]

Hi Kraal,

I've changed the ADC mode to synchronous and the jitter (on toggled GPIO) is reduced to 1.6us.

Okay. I'll also trying to measure the sampling as JW and you have suggested.

thanks,

gaston