// STM32F407VG, STM32F407ZG, STM32F405RG
// DO NOT EDIT! Automatically generated!
static void stm32f40x_usart_create_objects(Object *obj, JSON_Object *svd,
const char *name)
{
STM32USARTState *state = STM32_USART_STATE(obj);
JSON_Object *periph = svd_get_peripheral_by_name(svd, name);
svd_add_peripheral_properties_and_children(obj, periph, svd);
// Registers.
state->u.f4.reg.sr = cm_object_get_child_by_name(obj, "SR");
state->u.f4.reg.dr = cm_object_get_child_by_name(obj, "DR");
state->u.f4.reg.brr = cm_object_get_child_by_name(obj, "BRR");
state->u.f4.reg.cr1 = cm_object_get_child_by_name(obj, "CR1");
state->u.f4.reg.cr2 = cm_object_get_child_by_name(obj, "CR2");
state->u.f4.reg.cr3 = cm_object_get_child_by_name(obj, "CR3");
state->u.f4.reg.gtpr = cm_object_get_child_by_name(obj, "GTPR");
// SR bitfields.
state->u.f4.fld.sr.pe = cm_object_get_child_by_name(state->u.f4.reg.sr,
"PE");
state->u.f4.fld.sr.fe = cm_object_get_child_by_name(state->u.f4.reg.sr,
"FE");
state->u.f4.fld.sr.nf = cm_object_get_child_by_name(state->u.f4.reg.sr,
"NF");
state->u.f4.fld.sr.ore = cm_object_get_child_by_name(state->u.f4.reg.sr,
"ORE");
state->u.f4.fld.sr.idle = cm_object_get_child_by_name(state->u.f4.reg.sr,
"IDLE");
state->u.f4.fld.sr.rxne = cm_object_get_child_by_name(state->u.f4.reg.sr,
"RXNE");
state->u.f4.fld.sr.tc = cm_object_get_child_by_name(state->u.f4.reg.sr,
"TC");
state->u.f4.fld.sr.txe = cm_object_get_child_by_name(state->u.f4.reg.sr,
"TXE");
state->u.f4.fld.sr.lbd = cm_object_get_child_by_name(state->u.f4.reg.sr,
"LBD");
state->u.f4.fld.sr.cts = cm_object_get_child_by_name(state->u.f4.reg.sr,
"CTS");
.....
....
....
...
...
// GTPR bitfields.
state->u.f4.fld.gtpr.psc = cm_object_get_child_by_name(state->u.f4.reg.gtpr,
"PSC");
state->u.f4.fld.gtpr.gt = cm_object_get_child_by_name(state->u.f4.reg.gtpr,
"GT");
}
