I'm trying to set up UART9, And use it by DMA1. But I think that UART9 CLK are not enableת because of I didn't get any DMA1 Interrupt.

[ESega.1]

/* UART9 init function */

void MX_UART9_Init(void)

{

 /* USER CODE BEGIN UART9_Init 0 */

 /* USER CODE END UART9_Init 0 */

 LL_USART_InitTypeDef UART_InitStruct = {0};

 LL_GPIO_InitTypeDef GPIO_InitStruct = {0};

 LL_RCC_SetUSARTClockSource(LL_RCC_USART16_CLKSOURCE_PCLK2);

 /* Peripheral clock enable */

 __HAL_RCC_UART9_CLK_ENABLE();

 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOD);

 /**UART9 GPIO Configuration

 PD14  ------> UART9_RX

 PD15  ------> UART9_TX

 */

 GPIO_InitStruct.Pin = MAIN_UART_RX_Pin|MAIN_UART_TX_Pin;

 GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;

 GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;

 GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;

 GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;

 GPIO_InitStruct.Alternate = LL_GPIO_AF_11;

 LL_GPIO_Init(GPIOD, &GPIO_InitStruct);

 /* UART9 DMA Init */

 /* UART9_TX Init */

 LL_DMA_SetPeriphRequest(DMA1, LL_DMA_STREAM_0, LL_DMAMUX1_REQ_UART9_TX);

 LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_STREAM_0, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);

 LL_DMA_SetStreamPriorityLevel(DMA1, LL_DMA_STREAM_0, LL_DMA_PRIORITY_LOW);

 LL_DMA_SetMode(DMA1, LL_DMA_STREAM_0, LL_DMA_MODE_NORMAL);

 LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_STREAM_0, LL_DMA_PERIPH_NOINCREMENT);

 LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_STREAM_0, LL_DMA_MEMORY_INCREMENT);

 LL_DMA_SetPeriphSize(DMA1, LL_DMA_STREAM_0, LL_DMA_PDATAALIGN_BYTE);

 LL_DMA_SetMemorySize(DMA1, LL_DMA_STREAM_0, LL_DMA_MDATAALIGN_BYTE);

 LL_DMA_DisableFifoMode(DMA1, LL_DMA_STREAM_0);

 /* UART9_RX Init */

 LL_DMA_SetPeriphRequest(DMA1, LL_DMA_STREAM_1, LL_DMAMUX1_REQ_UART9_RX);

 LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_STREAM_1, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

 LL_DMA_SetStreamPriorityLevel(DMA1, LL_DMA_STREAM_1, LL_DMA_PRIORITY_LOW);

 LL_DMA_SetMode(DMA1, LL_DMA_STREAM_1, LL_DMA_MODE_NORMAL);

 LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_STREAM_1, LL_DMA_PERIPH_NOINCREMENT);

 LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_STREAM_1, LL_DMA_MEMORY_INCREMENT);

 LL_DMA_SetPeriphSize(DMA1, LL_DMA_STREAM_1, LL_DMA_PDATAALIGN_BYTE);

 LL_DMA_SetMemorySize(DMA1, LL_DMA_STREAM_1, LL_DMA_MDATAALIGN_BYTE);

 LL_DMA_DisableFifoMode(DMA1, LL_DMA_STREAM_1);

 /* USER CODE BEGIN UART9_Init 1 */

 /* USER CODE END UART9_Init 1 */

 UART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1;

 UART_InitStruct.BaudRate = 115200;

 UART_InitStruct.DataWidth = LL_USART_DATAWIDTH_9B;

 UART_InitStruct.StopBits = LL_USART_STOPBITS_1;

 UART_InitStruct.Parity = LL_USART_PARITY_EVEN;

 UART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;

 UART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;

 UART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;

 LL_USART_Init(UART9, &UART_InitStruct);

 LL_USART_DisableFIFO(UART9);

 LL_USART_SetTXFIFOThreshold(UART9, LL_USART_FIFOTHRESHOLD_1_8);

 LL_USART_SetRXFIFOThreshold(UART9, LL_USART_FIFOTHRESHOLD_1_8);

 LL_USART_ConfigAsyncMode(UART9);

 /* USER CODE BEGIN WKUPType UART9 */

 /* USER CODE END WKUPType UART9 */

 LL_USART_Enable(UART9);

 /* Polling UART9 initialisation */

 while((!(LL_USART_IsActiveFlag_TEACK(UART9))) || (!(LL_USART_IsActiveFlag_REACK(UART9))))

 {

 }

 /* USER CODE BEGIN UART9_Init 2 */

  LL_DMA_ConfigAddresses(DMA1, LL_DMA_STREAM_0,

             (uint32_t)aUart9TxBuffer,

             LL_USART_DMA_GetRegAddr(UART9, LL_USART_DMA_REG_DATA_TRANSMIT),

             LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_STREAM_0));

 LL_DMA_SetDataLength(DMA1, LL_DMA_STREAM_0, ubUart9NbDataToTransmit);

 LL_DMA_SetPeriphRequest(DMA1, LL_DMA_STREAM_0, LL_DMAMUX1_REQ_UART9_TX); 

 LL_DMA_SetMemoryAddress(DMA1, LL_DMA_STREAM_0,(uint32_t)aUart9TxBuffer);

 LL_DMA_SetPeriphAddress(DMA1, LL_DMA_STREAM_0,(uint32_t)&(UART9->TDR));

 LL_DMA_SetDataLength(DMA1, LL_DMA_STREAM_0,ubUart9NbDataToTransmit);

 LL_DMA_EnableIT_DME(DMA1, LL_DMA_STREAM_0);

 LL_DMA_EnableStream(DMA1, LL_DMA_STREAM_0);

 /* (2) Enable DMA transfer complete/error interrupts */

 LL_DMA_EnableIT_TC(DMA1, LL_DMA_STREAM_0);

 LL_DMA_EnableIT_TE(DMA1, LL_DMA_STREAM_0);

 /* USER CODE END UART9_Init 2 */

}

[Tesla DeLorean]

>>But I think that UART9 CLK are not enableת because of I didn't get any DMA1 Interrupt.

Well you for sure don't enable the DMA1 clock in the shown code.

In the 9-bit (8E1) mode, you might need WORD transactions.

Unclear which STM32 this involves.

[TDK]

In addition to not enabling the DMA1 clock, I don't see you enabling DMA requests on the peripheral side anywhere either.

[ESega.1]

Thanks, I'm using STM32H725IG

[ESega.1]

I set UART9 just like i use UART4.

UART4 work, UART9 Does not work.

[TDK]

Read out and report the values of the relevant UART and DMA registers at the end of the initialization.

[ESega.1]

Do these help?

 

[TDK]

Those values aren't consistent with the code you presented. The DMA1_S0M0AR register (among others) is 0 but clearly it's being set in the code:

>  LL_DMA_SetMemoryAddress(DMA1, LL_DMA_STREAM_0,(uint32_t)aUart9TxBuffer);

If the clock wasn't enabled, stream 2 values would be zero. Step through the code and verify these values are getting set on the appropriate line.

I could be missing something but don't think I am.

[waclawek.jan]

> If the clock wasn't enabled, stream 2 values would be zero.

That does not mean the clock is enabled while writing into Stream0 and Stream1.

JW

[TDK]

If the registers are shown at the end of the initialization code shown, it does. Which is what I requested. But it's entirely possible that's not where they were taken.

DMAT also isn't set on either UART4 or UART9, so it's unclear how UART4 is "working".

Lots of questions, not many answers.