2022-12-27 07:39 AM
#include <stdint.h>
#define RCC_CFGR_BASE_ADDR 0x40012800UL
#define RCC_CFGR_REG_OFFSET 0x04UL
#define RCC_CFGR_REG_ADDR (RCC_CFGR_BASE_ADDR + RCC_CFGR_REG_OFFSET )
#define RCC_APB2ENR_REG_OFFSET 0x18UL
#define RCC_APB2ENR_REG_ADDR (RCC_CFGR_BASE_ADDR + RCC_APB2ENR_REG_OFFSET )
#define GPIO_MODE_BASE_ADDR 0x40011000UL
#define GPIO_MODE_REG_OFFSET 0x04UL
#define GPIO_MODE_REG_ADDR (GPIO_MODE_BASE_ADDR + GPIO_MODE_REG_OFFSET )
#define GPIO_MODE_ODR_OFFSET 0x0CUL
#define GPIO_MODE_ODR_ADDR (GPIO_MODE_BASE_ADDR + GPIO_MODE_ODR_OFFSET )
int main(void)
{
uint32_t *pRccCfrReg = (uint32_t*)RCC_CFGR_REG_ADDR;
uint32_t *pRccApb2EnReg = (uint32_t*)RCC_APB2ENR_REG_ADDR ;
uint32_t *pGPIOModeReg = (uint32_t*)GPIO_MODE_REG_ADDR;
uint32_t *pGPIO_OdrReg = (uint32_t*)GPIO_MODE_ODR_ADDR;
*pRccCfrReg |= (0x5 << 23); // Selected HSI as clock bit position 24(1),25(0),26(1)
*pRccApb2EnReg = (0x1);// Pheriperal clock enable
*pGPIOModeReg = (0x22);// // Output mode, max speed 2 MHz. & 00: General purpose output push-pull
while(1)
{
*pGPIO_OdrReg = (0xfffff); //
// for(volatile uint32_t i =0; i<1000; i++)
// ;
// *pGPIO_OdrReg = (0x0);
}
}
2022-12-27 10:18 AM
Well, almost everything is wrong.
Have a look at some online tutorials on STM32 - there are plenty of them..
Use the ST-supplied header files and apply standard register access methods, like RCC->APB2ENR |= RCC_APB2ENR_GPIOAEN;
Dont turn on the HSI - it's already turned on and selected as clock source right after reset.
In the loop, turn the LED on, then wait for some resonable time, then turn it off, then wait again.
If writing the core completely by yourself is too difficult, then use STM32IDE to setup the peripherals and just write the blinking code.
2022-12-27 10:38 AM
When new at something perhaps better to start with the least complex approach not the most?
The GPIO address suggests BANK C, yet you enable clock only for BANK A
LEDs on the VL-Discovery are PC8 and PC9, not sure you're configuring the right outputs.
2022-12-28 12:12 AM
Corrected
The RCC base address was wrong
corrected as #define RCC_CFGR_BASE_ADDR 0x40021000UL
thanks