2023-01-07 06:29 PM
I found some bugs in the CubeMX generated code.
Does it forget reset the `state` after SDIO DMA TX? when I query the TX state by `HAL_SD_GetState` always get wrong result.
Dose SDIO DMA mode forget clear the transition state to SD card? when erase the block after a DMA read, it always failed, I have to put a `HAL_SD_Abort` after RX finished.
The follow code blocks forget `__DSB` sync instruction in function `HAL_NAND_Read_Status`, My MCU is stm32f746ig which with data cache, the origin version of code makes the MCU infinite loop.
Solved! Go to Solution.
2023-01-07 08:47 PM
Hi,
The "HAL" library is not a generated code, CubeMX/CubeIDE installs it as is.
The source of the library can be also found on github, and you can open a bug report there.
Read this before opening an issue.
When you wish to report a bug, first of all do mention versions of the software in use: Version of CubeMX/CubeIDE and version of the libraries. On github instead you can just point to a specific line and select "Reference in a new issue".
In your last snippet, the file name is stm32f4_hal_nand_c, though your MCU is F7. How this happened?
2023-01-07 08:47 PM
Hi,
The "HAL" library is not a generated code, CubeMX/CubeIDE installs it as is.
The source of the library can be also found on github, and you can open a bug report there.
Read this before opening an issue.
When you wish to report a bug, first of all do mention versions of the software in use: Version of CubeMX/CubeIDE and version of the libraries. On github instead you can just point to a specific line and select "Reference in a new issue".
In your last snippet, the file name is stm32f4_hal_nand_c, though your MCU is F7. How this happened?
2023-01-07 09:11 PM
sorry, I put the wrong file, but stm32f4_hal_nand_c has the same problem to stm32f7_hal_nand_c
2023-01-08 04:03 PM
The SDIO issue could be a bug or a similar issue to the one reported in this topic.
The NAND issue is a bug, but has nothing to do with a cache. Instructions can be reordered because the Cortex-M7 is a dual issue CPU and the respective NAND_DEVICE memory region by default is configured as a normal memory type. Read this article for a more detailed explanation. The solution - a single __DMB() macro between sending the command and reading the status (line 2368) is enough. And, of course, the same bug is present in F7 and H7 series HAL drivers.
Edited by moderating team to adhere to community guidelines