how can we send binary data on two different pins simultaneously on both the rising edge and falling edge of dclk whose speed can be 1MHz on stm32f4?

[SAMIN.1]

PCA is managed by a full-duplex serial interface. A typical data frame is defined by

a burst of 8 DCLK pulses followed by an assertion of a DLOAD pulse (these lines are driven by the host printing system.). During each frame, 32 bits of control or print data (16 bits each, on DIN_1 and DIN_2) are transferred from the host printing system. Input data (to the controller ASIC) is clocked on both the rising and falling edges of DCLK. 

I have also attached a waveform image.

I have also written a code, it works perfectly but the speed is too slow.

code:

HAL_GPIO_WritePin(DLOAD_GPIO_Port, DLOAD_Pin, GPIO_PIN_RESET);

  for (int i = 0; i < 8; i++)

  {

    c = din2 & 1;

    d = din1 & 1;

    uint16_t e = 0x0000;

    e = e | c;

    e = e << 1;

    e = e | d;

    din2 >>= 1;

    din1 >>= 1;

   GPIOB->ODR = e;               //Write to port-b

   HAL_GPIO_WritePin(DCLK_GPIO_Port, DCLK_Pin, GPIO_PIN_SET);

    c = din2 & 1;

    d = din1 & 1;

    e = 0x0000;

    e = e | c;

    e = e << 1;

    e = e | d;

    din2 >>= 1;

    din1 >>= 1;

   GPIOB->ODR = e;               //Write to port-b

   HAL_GPIO_WritePin(DCLK_GPIO_Port, DCLK_Pin, GPIO_PIN_RESET);

  }

therefore anyone can suggest a better method to implement the desired waveform.

Either SPI or I2c can be utilized or not. because both can transfer data on a single gpio pin.

[Paul1]

I have to say I've never seen a protocol that clocks on both edges, but it makes sense since if the clock can transition that often then the data at that "speed" should be able to get there as well.

Please provide some links for this protocol (or is it internal/proprietary?)

Possibilities:

1. Interrupts on both clock edges for reading/writing data

• If too slow try: Increase Interrupt Priority, Increase MCU Clock, Reduce datarate, write interrupt code in assembly,

2. Use DMA to Rx/Tx bunch data, with post/pre processing to arrange bits/bytes.

• May be wasteful of memory if using only 1 bit per byte. Possibly

3. Use a clock doubler/halver (Several options depending on existing circuits: FlipFlop, PLL, etc).

• For Clock Rx: By doubling the clock you could use regular SPI to Tx/Rx.
• For Clock Tx: By halving the clock the other end can clock on both edges.

(Serve me some rum and I'll have more ideas)

Paul

[Tesla DeLorean]

Perhaps use TIM in Input Capture, capture both edges, have the capture generate a DMA request, service that as a write to GPIO->BSRR or ODR from a pattern buffer.

[Paul1]

Concern: Jitter

• Is this unidirectional data, or restricted to systems with both ends very close together (inches)?
• I'd be concerned with clocking the Tx and Rx on the same edge, as any clock jitter or delay could cause one end to Rx while the data is in Tx transition from other end, if the Rx end is seeing even a slightly delayed clock.
• This could be worse if implemented in code, as any "if" paths in the code will introduce jitter. In code need to ensure all paths are exactly same clock cycles, either (a) receive data without any "IF paths and then post process, or (b) pad out all code paths to exact same timing using NOPs.

Paul

[waclawek.jan]

Use timer to generate clocks: using PWM mode to generate single-edge clock on one channel and Toggle mode to generate double-edge clock (DCLK for the target) on second channel. Connect externally the single-edge clock to SCK pins of two SPI modules set as slave and preloaded by data, and run the timer to generate 16 single-edge clocks = 8 double-edge clocks (e.g. using TIM1/TIM8 with RCR set to 16 and One-Pulse mode).

JW

[MM..1]

Your code is extreme unefective. Too you dont write MCU type and clock. Normal M0 gpio can handle 25MHz and M4 90MHz ... And maybe perfect for you is DDR QSPI mode.

[SAMIN.1]

Serial Data Transfer Protocol:

Communication between the host printing system and the controller ASIC on the PCA is managed by a full-duplex serial interface. A typical data frame is defined by a burst of 8 DCLK pulses followed by assertion of a DLOAD pulse (these lines are driven by the

host printing system.). During each frame, 32 bits of control or print data (16 bits each, on DIN_1

and DIN_2) are transferred from the host printing system. Then 8 bits of status or measurement

data are returned to the host printing system from the controller ASIC. Input data (to the controller

ASIC) is clocked on both the rising and falling edges of DCLK. Output data is clocked on the falling

edge of DCLK and should be latched in by the host printing system on the rising edge (BIT 0 of the

output data word is placed on the DOUT line in response to DLOAD transitioning low at the end of

the previous frame.).

A low-to-high transition of DLOAD causes status or measurement data within the controller ASIC to

be latched into the output shift register and Bit 0 of the output data word to be placed on the DOUT

line. While DLOAD is in the high state, the internal DCLK counter in the controller ASIC is halted

and the I/O shift registers are disabled. When DLOAD returns to a logic low, the contents of the

controller ASIC input shift registers are transferred to the appropriate control or print data registers.

If the input data word is a control word and contains a valid analog-to-digital converter channel

address, the falling edge of DLOAD will also initiate A/D conversion.

It is imperative that there be no more or no less than eight (8) rising and falling **** edges while

DLOAD is low. This will prevent data corruption due to under-run or over-run of the driver ASIC

input shift registers. Any extraneous transitions (such as gating spikes) that occur on the DCLK line

when DLOAD is in the low state will be interpreted as valid clock edges and must be avoided. This

is important during transfers of print data blocks where false clocking can cause print data words

(DIN_1 LSB=0) to be interpreted as command words (DIN_1 LSB=1).

this is the whole serial transfer protocol. my code is too slow as DCLK can be set at max 5.33Mhz.

DIN1 and DIN2 are the input for the ASIC. but for microcontrollers, they act act as outputs(DIN1 and DIN2). I have to transfer data from DIN1 and DIN2 to ASIC at max speed.

but I am unable to do that.

i am using STM32F407. Microcontroller clock(HCLK) = 150Mhz.

TIM1 is used for microsecond delay.

TIM2 is used for nanosecond delay.

TIM3 is used for PWM.

TIM8 is used for ENCODER.

.

[SAMIN.1]

I need to send data through DIN1 and DIN2 to ASIC.

so how input capture can be used?

[SAMIN.1]

MCU Clock = 150Mhz.

Maybe it will take a lot of memory. As data can be Mbyte long to process.

[SAMIN.1]

my code is ineffective, that's why it takes much time. I am using STM32F407 which does to have QSPI mode.

I need alternative ideas to solve my problem.