2019-11-06 06:52 PM
In 15.5.12, the register definition for mdma_ctbr , i am having trouble understanding the dbus and sbus bit descriptions. Shouldn't the choices be between tcm/axi and ahb/system and not system/axi and ahb/tcm as the latter is mixing the domains together and is thus meaningless? which is which? Wouldn't it be clearer if the choice was D1 or D2?
Thanks.
2019-11-07 01:31 AM
TCM is not in D1 nor D2 domain, it's an exception not going through the bus matrices but a dedicated interconnection between MDMA and the AHBS port of processor - and it's a 32-bit bus. So the description might rather be "64/32 bit" or "AXI/non-AXI".
JW
2019-11-07 04:40 AM
Thank you for the clarification. In looking deeper into what i was doing, i realized it was wrong anyway. I was trying to use mdma and dma to get single chars from uart5 to tcm which seemed weird and cumbersome. I have switched to using dma2 handled by the m4 core to store the incoming bytes in a ram3 buffer and using mdma memory to memory to copy the buffer to tcm. I already have the code to exchange data between the two cores via mdma, so i just changed it so that the rx data is copied to the m7 not from it.