I've been looking at the information on the flash organization in the Reference manual RM0456 for STM32U5. In particular I'm trying to understand how the DUALBANK flag works on this family.
In section 7.3.1, there is this table for STM32U5G with 4MB of internal flash
In the note (1) it mentions that with DUALBANK = 1 in option bytes (which should be the default as far as I have understood), the base address for bank 2 is 0x0810_0000. But this means that bank 1 is now only 1MB. So are the two banks overlapped?
Also it is not clear to me what happens to the page size when using dual/single bank? Is it doubled?
I have seen that there is an application note for the F7 family, but I don't understand if the U5 family works the same
Could someone please give me some additional details on how DUALBANK flag works on this family or point me to some documentation that better describes this feature?
In dual bank mode, the flash memory is divided into two banks, each with its own base address.
For 2MB flash, Bank 1 is from 0x0800 0000 to 0x080F FFFF and Bank 2 is from 0x0810 0000 to 0x081F FFFF.
For 4MB flash, Bank 1 is from 0x0800 0000 to 0x081F FFFF and Bank 2 is from 0x0820 0000 to 0x083F FFFF.
Thanks for the feedback FBL. It was really helpful!!
I totally overlooked the fact that those chips can have either 2 or 4 MB of flash. Now that makes sense.
Can you please also provide additional details on what changes setting DUALBANK flag to 0/1? I could only find this in the reference manual and it is not really clear what happens in terms of addressing and page size on the U5
