DAC with Timer

[GKIM.4]

Hello!​

I am using b-l475e-iot01a1, and I am currently working on DAC using Timer and DMA.

DAC uses Ch1 of DAC1 and Timer uses TIM2.

The TRGO of TIM2 is Update Event, and the Trigger of DAC is using TIM2 Trigger Out Event.

Sine function values from 64 samples are exported to DAC, and you want to set the frequency of the sine function to 200 Hz.

To do this, you want to set the TIM2 to 12.8 KHz (200 X 64 Hz).

The current APB1 Timer Clock is 80 MHz.

Therefore, Prescaler set 125-1 and Counter Period set 250-1. (80000 KHz / (25 X 250) = 12.8 KHz)

However, the frequency of the DAC is not 200 Hz, but 205 Hz.

What's the problem?

[LCE]

Timer settings make sense.

What's the clock source, HSI or HSE ?

The internal RC oscillator (HSI) is not that exact and quite jittery.

Does that STM32 have some HSI calibration options / registers?

[Simon.T]

Hello @GKIM.4​ ,

I tried your solution (sinusoid generation using DAC and DMA) on STM32 H7 using the same frequency (FAPB1=80MHz):

I recalculate the prescaler and the counter period. I used:

PSC=24

Counter period=250.

And with 64 samples I obtain the right frequency (200Hz).

Nevertheless I also checked with 63 samples and I obtained the same result as you (~205Hz). Are you sure you tried with the right samples number ?

If you need I can share you my sine buffer.

Best regards,

Simon TALAS

[Simon.T]

Hello @Community member​,

The HSI with the PLL is not precise at 100%, otherwise the jitter of the PLL is about +- 40ps. Therefore for 80MHz the frequency out of the PLL will move between 79.74482MHz and 80.25682MHz for some periods.

If we take the worst case : 40ps jitter at each clock pulse (commonly not the case, jitter is dynamic). Thus for a sinewave at 200Hz we can get a maximum of 200.64Hz and a minimum of 199.36Hz.

Then, the relation between HSI/PLL and the frequency error measured are not related.

Best regards,

Simon

[GKIM.4]

Thanks for comment.

I am a beginner about STM32.

And, I don't know about HSI or HSE.

So, your comment is very helpful.

I'll check my workbench.

Thank you.

[GKIM.4]

Thanks for comment.

I checked that the number of samples is 64.

But I know that TIM frequency ​is decided APB1 / ((PSC + 1) * (Period + 1).

Is this wrong?

Counter period of yours is set 250.

So, TIM frequency is 80MHz / ((24+1) * (250 +1)), 12.749 KHz.

And 64 sample DAC output is about 199.2 Hz.

Am I wrong?​

[LCE]

@Simon.T​ 

I didn't mean that the HSI jitter might cause this constant error, that was just a side hint that using HSI for signal generation might not be a good idea.

I once tried that for SPDIF signals (F767) and the results were terrible.

@GKIM.4​ 

Check your clock source (CubeMX clock config tree, or void SystemClock_Config(void) , or even better directly the RCC register and compare to datasheet), if you are using

HSI: High Speed Internal, the inaccurate internal RC oscillator, or

HSE: some external clock source, a quarz, or maybe MCO from the STlink MCU, so even that one is not safe to be accurate.

For tuning the HSI:

https://www.st.com/resource/en/application_note/dm00425536-how-to-optimize-stm32-mcus-internal-rc-oscillator-accuracy-stmicroelectronics.pdf

[LCE]

@GKIM.4​ 

Can you use the clock output MCO to check the clock's basic accuracy?

I think you're right with PSC -1 and ARR -1 register settings.

[GKIM.4]

Thanks for comment.

I don't think that check the clock output.

I'll check the clock output MCO.

But RCC_MCO is assigned to only PA8 that is assigned to contol of RF module on B-L475E-IOT01A1.

Thank you.

[Simon.T]

Yes, you are right. I made a typo, the counter period is set a 249 to have 12.8kHz.

Otherwise to check if the counter frequency is ok (and at the same time the HSI accuracy) you can measure it with the PWM.

To do this, you should select PWM Generation on Channel(1-3), set the pulse value at 125 and measure it on the GPIO